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distinguishing features single-chip composite/s-video ntsc/pal/secam to ycrcb digitizer on-chip ultralock ? square pixel and ccir601 resolution for: ntsc (m) ntsc (m) without 7.5ire pedestal pal (b, d, g, h, i, m, n, n combination) secam chroma comb ?ter arbitrary horizontal and 5-tap vertical ?tered scaling hardware closed-caption decoder vertical blanking interval (vbi) data pass-through arbitrary temporal decimation for a reduced frame-rate video sequence programmable hue, brightness, saturation, and contrast user-programmable cropping of the video window 2x oversampling to simplify external analog ?tering two-wire inter-integrated circuit (i 2 c) bus interface 8- or 16-bit pixel interface ycrcb (4:2:2) output format software selectable four-input analog mux 4 fully programmable gpio bits auto ntsc/pal format detect automatic gain control (agc) typical power consumption 0.85 w ieee 1149.1 joint test action group (jtag) interface 100-pin pqfp and tqfp packages related products bt819a, bt829, bt856/857, bt864/865, bt866/867, bt852 applications multimedia image processing desktop video video phone teleconferencing interactive video adc ultralock and clock mux0 mux1 muxout syncdet refout yref+ yin 16 decimation lpf output luma-chroma separation and chroma output video yref output formatting analog mux adc cref+ cin cref agc timing control data i 2 c jtag demodulation spatial and temporal scaling video timing unit generation xt0 xt1 40 mhz 40 mhz mux2 advance information this document contains information on a product under development. the para- metric information contains target parameters that are subject to change. mux3 videostream ii decoders bt829a/827a bt829a video capture processor & scaler for tv/vcr analog input BT827A composite video and s-video decoder the bt829a and BT827A videostream decoders are a family of single-chip, pin- and register-compatible, composite ntsc/pal/secam video and s-video decod- ers. they are also pin and register backward compatible with the bt829/827 family of products. low operating power consumption and power-down capability make them ideal low-cost solutions for pc video capture applications on both desktop and portable system platforms. they support square pixel and ccir601 resolutions for ntsc, pal and secam video. they have a ?xible pixel port which supports a variety of system interface con?urations, and they are offered in 100-pin pqfp and 100-pin tqfp packages. functional block diagram
cop yright ?1997 rockwell semiconductor systems. all rights reserv ed. print date: november, 1997 rockwell reserv es the right to mak e changes to its products or speci cations to impro v e performance, reliability , or manuf acturability . information furnished by rockwell semiconductor systems is belie v ed to be accurate and reliable. ho we v er , no responsibility is assumed by rockwell semiconductor systems for its use; nor for an y infringement of patents or other rights of third parties which may result from its use. no license is granted by its implication or otherwise under an y patent or patent rights of rockwell semiconductor systems. rockwell products are not designed or intended for use in life support appliances, de vices, or systems where malfunction of a rockwell product can reasonably be e xpected to result in personal injury or death. rockwell customers using or selling rockwell products for use in such applications do so at their o wn risk and agree to fully indemnify rockwell for an y damages resulting from such improper use or sale. bt is a re gistered trademark of rockwell semiconductor systems. product names or services listed in this publication are for identi cation purposes only , and may be trademarks or re gistered trademarks of their respecti v e companies. all other marks mentioned herein are the property of their respecti v e holders. speci cations are subject to change without notice. printed in the united states of america ordering information model number package ambient temperature range bt829akrf 100-pin pqfp 0?c to +70?c BT827Akrf 100-pin pqfp 0?c to +70?c bt829aktf 100-pin tqfp 0?c to +70?c
iii l829a_b t able of c ontents list of figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . viii list of t ab les . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . x functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 functional over vie w . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 bt829a video capture processor f or tv/vcr analog input . . . . . . . . . . . . . . . . . . . . 3 BT827A composite/s-video decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 bt829a architecture and p ar titioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ultr aloc k ? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 scaling and cropping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 input interf ace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 output interf ace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 vbi data p ass-through . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 closed caption decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 i 2 c interf ace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 diff erences between bt829/827 and bt829a/827a . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 ultraloc k . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 the challenge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 oper ation pr inciples of ultr aloc k . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 composite video input formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 y/c separation and chr oma demodulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 video scaling, cr opping, and t emporal decimation . . . . . . . . . . . . . . . . . . . . . . . . . . 18 hor iz ontal and v er tical scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 luminance scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 p eaking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 chrominance scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 scaling registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 image cropping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 cropping registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 t empor al decimation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
iv l829a_b bt829a/827a v ideostr eam ii decoders t able of c ontents video adjustments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 the hue adjust register (hue) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 the contr ast adjust register (contrast) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 the satur ation adjust registers (sa t_u , sa t_v) . . . . . . . . . . . . . . . . . . . . . . . . . . 31 the br ightness register (bright) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 bt829a vbi data output interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 ov er vie w . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 functional descr iption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 vbi line output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 vbi f r ame output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 closed captioning and extended data ser vices decoding . . . . . . . . . . . . . . . . . . . . 39 a utomatic chrominance gain control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 lo w color detection and remo v al . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 cor ing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 electrical interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 input interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 analog signal selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 multiple x er consider ations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 a utodetection of ntsc or p al/secam video . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 flash a/d con v er ters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 a/d clamping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 p o w er-up oper ation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 a utomatic gain controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 cr ystal inputs and cloc k gener ation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 2x ov ersampling and input filter ing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 output interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 output interf aces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 ycrcb pix el stream f or mat, spi mode 8- and 16-bit f or mats . . . . . . . . . . . . . . . . . 51 synchronous pix el interf ace (spi, mode 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 synchronous pix el interf ace (spi, mode 2, bytestream) . . . . . . . . . . . . . . . . . . . 54 ccir601 compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 i 2 c interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 star ting and stopping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 addressing the bt829a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 reading and wr iting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 softw are reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
v l829a_b t able of c ontents bt829a/827a v ideostr eam ii decoders jt a g interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 need f or functional v er i cation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 jt a g approach to t estability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 optional de vice id register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 v er i cation with the t ap controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 example bsdl listing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 pc boar d la y out considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 ground planes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 p o w er planes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 supply decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 digital signal interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 analog signal interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 latch-up a v oidance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 sample schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
vi l829a_b bt829a/827a v ideostr eam ii decoders t able of c ontents contr ol register de nitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 0x00 ?de vice status register (st a tus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 0x01 ?input format register (iform) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 0x02 ? t emporal decimation register (tdec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 0x03 ?msb cr opping register (cr op) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 0x04 ? v er tical dela y register , lo wer byte (vdela y_lo) . . . . . . . . . . . . . . . . . . . . . 84 0x05 ? v er tical active register , lo wer byte (v a ctive_lo) . . . . . . . . . . . . . . . . . . . 85 0x06 ?horizontal dela y register , lo wer byte (hdela y_lo) . . . . . . . . . . . . . . . . . . 86 0x07 ?horizontal active register , lo wer byte (ha ctive_lo) . . . . . . . . . . . . . . . . 87 0x08 ?horizontal scaling register , upper byte (hscale_hi) . . . . . . . . . . . . . . . . . 88 0x09 ?horizontal scaling register , lo wer byte (hscale_lo) . . . . . . . . . . . . . . . . 89 0x0a ?brightness contr ol register (bright) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 0x0b ?miscellaneous contr ol register (contr ol) . . . . . . . . . . . . . . . . . . . . . . . . . 91 0x0c ?luma gain register , lo wer byte (contrast_lo) . . . . . . . . . . . . . . . . . . . . 92 0x0d ?chr oma (u) gain register , lo wer byte (sa t_u_lo) . . . . . . . . . . . . . . . . . . . 93 0x0e ?chr oma (v) gain register , lo wer byte (sa t_v_lo) . . . . . . . . . . . . . . . . . . . 94 0x0f ?hue contr ol register (hue) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 0x10 ? sc loop contr ol (scloop) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 0x11 ? white crush up count register (wc_up) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 0x12 ?output format register (oform) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 0x13 ? v er tical scaling register , upper byte (vscale_hi) . . . . . . . . . . . . . . . . . . 101 0x14 ? v er tical scaling register , lo wer byte (vscale_lo) . . . . . . . . . . . . . . . . . . 102 0x15 ? t est contr ol register (test) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 0x16 ? video timing p olarity register (vpole) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 0x17 ?id code register (idcode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 0x18 ?a gc dela y register (adela y) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 0x19 ?bur st dela y register (bdela y) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 0x1a ?adc interface register (adc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 0x1b ? video timing contr ol (vtc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 0x1c ?extended data ser vice/closed caption status register (cc_st a tus) . 111 0x1d ?extended data ser vice/closed caption data register (cc_d a t a) . . . . . 113 0x1e ? white crush do wn count register (wc_dn) . . . . . . . . . . . . . . . . . . . . . . . . 114 0x1f ?software reset register (sreset) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 0x3f ?pr ogrammab le i/o register (p_io) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
vii l829a_b t able of c ontents bt829a/827a v ideostr eam ii decoders p arametric inf ormation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 dc electrical p arameter s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 a c electrical p arameter s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 p ac ka g e mec hanical dra wings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 re vision histor y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
viii l829a_b bt829a/827a v ideostr eam ii decoders l ist of f igures list of figures figure 1. bt829a/827a detailed block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 figure 2. bt829a/7a pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 3. ultr aloc k beha vior f or ntsc square pix el output . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 4. y/c separation and chroma demodulation for composite video . . . . . . . . . . . . . . . . . . 16 figure 5. y/c separation filter responses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 6. filtering and scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 7. optional horizontal luma low-pass filter responses . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 8. combined luma notch, 2x oversampling and optional low-pass filter response (ntsc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 9. combined luma notch, 2x oversampling and optional low-pass filter response (pal/secam) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 10. frequency responses for the four optional vertical luma low-pass filters . . . . . . . . . 20 figure 11. combined luma notch and 2x oversampling filter response . . . . . . . . . . . . . . . . . . . . 20 figure 12. p eaking filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 13. luma p eaking filters with 2x ov ersampling filter and luma notch . . . . . . . . . . . . . . . . . 22 figure 14. effect of the cropping and active registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 15. regions of the video signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 16. regions of the video f r ame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 17. bt829a ycrcb 4:2:2 data p ath . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 18. bt829a vbi data p ath . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 19. vbi line output mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 20. vbi sample region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 21. location of vbi data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 22. vbi sample order ing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 23. cc/eds data processing path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 24. cc/eds incoming signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 25. closed captioning/extended data ser vices fifo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 26. cor ing map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 27. bt829a typical external circuitry for backward compatibility with bt829/827 . . . . . . . . . 45 figure 28. bt829a typical external circuitry (reduced passive components) . . . . . . . . . . . . . . . . . 46 figure 29. clock options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 figure 30. luma and chroma 2x oversampling filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 31. output mode summar y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 figure 32. ycrcb 4:2:2 pix el stream f or mat (spi mode , 8 and 16 bits) . . . . . . . . . . . . . . . . . . . . . 52 figure 33. bt829a/827a synchronous pix el interf ace , mode 1 (spi-1) . . . . . . . . . . . . . . . . . . . . . . . 53 figure 34. basic timing relationships for spi mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 35. data output in spi mode 2 (bytestream) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
ix l829a_b l ist of f igures bt829a/827a v ideostr eam ii decoders figure 36. video timing in spi modes 1 and 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 figure 37. horizontal timing signals in the spi modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 figure 38. the relationship betw een scl and sd a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 figure 39. i 2 c sla v e address con gur ation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 figure 40. i 2 c protocol diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 figure 41. instr uction register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 figure 42. example ground plane la y out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 figure 43. optional regulator circuitr y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 figure 44. typical power and ground connection diagram and parts list . . . . . . . . . . . . . . . . . . . 69 figure 45. bt829/cirrus logic 544x vga interface schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 figure 46a. bt829/s3 virge 8-bit interface schematic - video input detail . . . . . . . . . . . . . . . . . . . . 72 figure 46b. bt829/s3 virge 8-bit interface schematic - bt829 detail . . . . . . . . . . . . . . . . . . . . . . . . . 73 figure 47a. bt829/trident vga interface schematic - tv tuner and video input detail . . . . . . . . . . 74 figure 47b. bt829/trident vga interface schematic - bt829 detail . . . . . . . . . . . . . . . . . . . . . . . . . . 75 figure 47c. bt829/trident vga interface schematic - feature connector detail . . . . . . . . . . . . . . . . 76 figure 48. clock timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 figure 49. output enable timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 figure 50. jtag timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 figure 51. 100-pin tqfp package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
x l829a_b bt829a/827a v ideostr eam ii decoders l ist of t ables list of t ab les table 1. videostream ii features options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 t ab le 2. pin descr iptions grouped by pin function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 t ab le 3. register diff erences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 4. video input formats supported by the bt829a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 t ab le 5. register v alues f or video input f or mats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 t ab le 6. scaling ratios f or p opular f or mats using f requency v alues . . . . . . . . . . . . . . . . . . . . . . 24 t ab le 7. pix el/pin map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 8. description of the control codes in the pixel stream . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 9. data output ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 10. bt829a address matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 t ab le 11. example i 2 c data t r ansactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 12. device identification register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 t ab le 13. register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 t ab le 14. recommended oper ating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 t ab le 15. absolute maxim um ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 t ab le 16. dc char acter istics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 t ab le 17. cloc k timing p ar ameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 t ab le 18. p o w er supply current p ar ameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 t ab le 19. output enab le timing p ar ameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 t ab le 20. jt a g timing p ar ameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 t ab le 21. decoder p erf or mance p ar ameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 t ab le 22. bt829a datasheet re vision histor y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
1 l829a_b f unctional d escription functional over vie w rockwell s v ideostream ? ii products are a f amily of single-chip, pin-and re gis- ter -compatible solutions for processing analog ntsc/p al/secam video into digital 4:2:2 ycrcb video. the y pro vide a comprehensi v e choice of capabilities to enable the feature set and cost to be tailored to dif ferent system hardw are con gu- rations. all solutions are housed in a 100-pin qfp package. a detailed block dia- gram is sho wn in figure 1 .
bt829a/827a v ideostr eam ii decoders 2 f unctional d escription functional over vie w l829a_b figure 1. bt829a/827a detailed bloc k dia gram muxout mux0 mux1 xt1o xt1i xt0o xt0i clkx1 clkx2 rst sd a i2ccs scl qclk hreset vreset a ctive field cbfla g d v alid video scaling input interf ace output interf ace y/c separ ation and chroma demodulation video i 2 c interf ace oe vd[15:8] vd[7:0] syncdet a gccap refout yref yin yref+ cref cin cref+ clevel cloc k interf ace jt a g interf ace and cropping adjustments c a/d y a/d ov ersampling lo w-p ass filter y/c separ ation chroma demod hue , satur ation, and br ightness adjust hor iz ontal and v er tical filter ing and scaling output f or matting video timing control i 2 c cloc king jt a g tdo tdi tms tck trst mux2 ccv alid v a ctive agc and mux3 sync detect
3 f unctional d escription functional over vie w l829a_b bt829a/827a v ideostr eam ii decoders bt829a video capture pr ocessor f or tv/vcr analog input the bt829a v ideo capture processor is a fully inte grated single-chip decoding and scaling solution for analog ntsc/p al/secam input signals from tv tuners, vcrs, cameras, and other sources of composite or y/c video. it is the second gen- eration front-end input solution for lo w-cost pc video/graphics systems that deli v- er complete inte gration and high-performance video synchronization, y/c separation, and ltered scaling. the bt829a has all the mix ed signal and dsp cir - cuitry required to con v ert an analog composite w a v eform into a scaled digital vid- eo stream, supporting a v ariety of video formats, resolutions, and frame rates. BT827A composite/s-video decoder the BT827A pro vides full composite and s-v ideo capability along with ltered horizontal scaling. v ertical scaling can only be implemented by line-dropping. the synchronous pix el interf ace (spi) is common to both pin-compatible de- vices, which enables implementation of a single system hardw are design. similar - ly , a common i 2 c re gister set allo ws a single piece of dri v er code to be written for softw are control of both options. t able 1 compares bt829a and BT827A features. bt829a ar c hitecture and p ar titioning the bt829a has been de v eloped to pro vide the most cost-ef fecti v e, high-quality video input solution for lo w-cost multimedia subsystems that inte grate both graph- ics display and video capabilities. the feature set of the bt829a supports a vid- eo/graphics system partitioning which optimizes the total cost of a system con gured both with and without video capture capabilities. this enables system v endors to easily of fer products with v arious le v els of video support using a single base-system design. as graphics chip v endors mo v e from graphics-only to video/graphics coproces- sors and e v entually to single-chip video/graphics processor implementations, the ability to ef ciently use silicon and package pins to support both graphics acceler - ation, video playback acceleration, and video capture becomes critical. this prob- lem becomes more acute as the race to w ards higher performance graphics requires more and more package pins to be consumed for wide 64-bit memory interf aces and glueless local b us interf aces. t ab le 1. videostream ii features options feature options bt829a BT827A composite video decoding x x s-video decoding x x secam video x x hardw are closed caption decode x x filtered v er tical scaling x
bt829a/827a v ideostr eam ii decoders 4 f unctional d escription functional over vie w l829a_b the bt829a minimizes the cost of video capture function inte gration in tw o w ays. first, recognizing that ycrcb to rgb color space con v ersion is a required feature of multimedia controllers for acceleration of digital video playback, the bt829a a v oids redundant functionality and allo ws the do wnstream controller to perform this task. second, the bt829a can minimize the number of interf ace pins required by a do wnstream multimedia controller in order to k eep package costs to a minimum. controller systems designed to tak e adv antage of these features allo w video capture capability to be added to the base system in a modular f ashion using only a single inte grated circuit (ic). the BT827A is tar geted at system con gurations using video processors which typically inte grate the scaling function. ultraloc k ? the bt829a and BT827A emplo y a proprietary technique kno wn as ultralock to lock to the incoming analog video signal. it will al w ays generate the required num- ber of pix els per line from an analog source in which the line length can v ary by as much as a fe w microseconds. ultralock s digital locking circuitry enables the v ideostream decoders to quickly and accurately lock on to video signals, re- g ardless of their source. since the technique is completely digital, ultralock can recognize unstable signals caused by vcr headswitches or an y other de viation and adapt the locking mechanism to accommodate the source. ultralock uses nonlinear techniques which are dif cult, if not impossible, to implement in gen- lock systems. and unlik e linear techniques, it adapts the locking mechanism auto- matically . scaling and cr opping the bt829a can reduce the video image size in both horizontal and v ertical direc- tions independently using arbitrarily selected scaling ratios. the x and y dimen- sions can be scaled do wn to one-sixteenth of the full resolution. horizontal scaling is implemented with a 6-tap interpolation lter , while up to 5-tap interpolation is used for v ertical scaling with a line store. the BT827A supports v ertical scaling by line-dropping. the video image can be arbitrarily cropped by programming the a ctive ag to reduce the number of acti v e scan lines and acti v e horizontal pix els per line. the bt829a and BT827A also support a temporal decimation feature that reduc- es video bandwidth by allo wing frames or elds to be dropped from a video se- quence at re gular b ut arbitrarily selected interv als. input interface analog video signals are input to the bt829a/827a via a four -input multiple x er that can select between four composite source inputs or between three composite and a single s-v ideo input source. when an s-v ideo source is input to the bt829a, the luma component is fed through the input analog multiple x er , and the chroma component is fed directly into the c input pin. an a gc circuit enables the bt829a/827a to compensate for reduced amplitude in the analog signal input.
5 f unctional d escription functional over vie w l829a_b bt829a/827a v ideostr eam ii decoders the clock signal interf ace consists of tw o pairs of pins for crystal connection and tw o clock output pins. one pair of crystal pins is for connection to a 28.64 mhz (8*ntsc fsc) crystal which is selected for ntsc operation. the other is for p al operation with a 35.47 mhz (8*p al fsc) crystal. either of the tw o crys- tal frequencies can be selected to generate clkx1 and clkx2 output signals. clkx2 operates at the full crystal frequenc y (8*fsc) whereas clkx1 operates at half the crystal frequenc y (4*fsc). either fundamental or third harmonic crystals may be used. alternati v ely , cmos oscillators may be used. output interface the bt829a and BT827A support a synchronous pix el interf ace (spi) mode. the spi supports a ycrcb 4:2:2 data stream o v er an 8- or 16-bit-wide path. when the pix el output port is con gured to operate 8 bits wide, 8 bits of chromi- nance data are output on the rst clock c ycle follo wed by 8 bits of luminance data on the ne xt clock c ycle for each pix el. t w o clocks are required to output one pix el in this mode, thus a 2x clock is used to output the data. the bt829a/827a outputs all horizontal and v ertical blanking pix els in addi- tion to the acti v e pix els synchronous with clkx1 (16-bit mode) or clkx2 (8-bit mode). it is also possible to insert control codes into the pix el stream using chromi- nance and luminance v alues that are outside the allo w able chroma and luma rang- es. these control codes can be used to ag video e v ents such as a ctive, hreset , and vreset . decoding these video e v ents do wnstream enables the vid- eo controller to eliminate pins required for the corresponding video control sig- nals. vbi data p ass-thr ough the bt829a/827a pro vides vbi data passthrough capability . the vbi re gion an- cillary data is captured by the video decoder and made a v ailable to the system for subsequent softw are processing. the bt829a/827a may operate in a vbi line output mode, in which the vbi data is only made a v ailable during select lines. this mode of operation is intended to enable capture of vbi lines containing an- cillary data as well as processing normal ycrcb video image data. in addition, the bt829a/827a supports a vbi frame output mode, in which e v ery line in the video signal is treated as if it w as a v ertical interv al line and no image data is output. this mode of operation is designed for use in still-frame capture/processing applica- tions. closed caption decoding the bt829a and BT827A pro vide a closed captioning (cc) and extended data services (eds) decoder . data presented to the video decoder on the cc and eds lines is decoded and made a v ailable to the system through the cc_d a t a and ccst a tus re gisters. i 2 c interface the bt829a/827a re gisters are accessed via a tw o-wire i 2 c interf ace. the bt829a/827a operates as a sla v e de vice. serial clock and data lines, scl and sd a, transfer data from the b us master at a rate of 100 kbits/s. chip select and re- set signals are also a v ailable to select one of tw o possible bt829a/827a de vices in the same system and to set the re gisters to their def ault v alues.
bt829a/827a v ideostr eam ii decoders 6 f unctional d escription pin descriptions l829a_b pin descriptions figure 2 details the bt829a and BT827A pinout. t able 2 pro vides pin numbers, names, input and output functions, and descriptions. figure 2. bt829a/7a pinout 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 numxtal vreset field gnd vdd agnd clevel cref vaa agnd n/c n/c n/c cin agnd vaa cref+ n/c yref agnd vaa syncdet agnd mux[1] agnd mux[0] agnd muxout yin n/c gnd clkx2 oe clkx1 vdd gnd gnd qclk pwrdn cbflag ccvalid vactive oepole dvalid active hreset gnd tdo gnd tck trst tms tdi vdd gnd vpos agccap vneg refout vaa mux[2] n/c agnd vaa yref+ mux[3] vdd vd[15] vd[14] vd[13] vd[12] vd[11] vd[10] vd[9] vd[8] vdd gnd vd[7] vd[6] vd[5] vd[4] vd[3] vd[2] vd[1] vd[0] vdd gnd xt0i xt0o rst xt1i xt1o sda scl i2ccs vdd gnd vdd gnd vdd bt829a/827a
7 f unctional d escription pin descriptions l829a_b bt829a/827a v ideostr eam ii decoders t ab le 2. pin descriptions gr ouped by pin function (1 of 4) pin # i/o pin name description input sta g e pins 45, 50, 55, 57 i mux[3:0] analog composite video inputs to the on-chip input m ultiple x er . the y are used to select betw een f our composite sources or three composite and one s-v ideo source . un used pins should be connected to gnd . 53 o muxout the analog video output of the 4-to-1 m ultiple x er . connected to the yin pin. 52 i yin the analog composite or luma input to the y -adc . 67 i cin the analog chroma input to the c-adc . 59 i syncdet the sync str ipper input gener ates timing inf or mation f or the a gc circuit. can be optionally connected through a 0.1 m f capacitor to the same source as the y -adc , to maintain compatibility with bt829 board la y outs . a 1 m w b leeder resistor can be con- nected to g round, to maintain compatibility with bt829 board la y outs . f or ne w bt829a designs , this pin ma y be connected to v aa. 41 a a gccap the a gc time constant control capacitor node . must be connected to a 0.1 m f capacitor to g round. 43 o refout output of the a gc which dr iv es the yref+ and cref+ pins . 49 a yref+ the top of the ref erence ladder of the y -adc . this should be connected to refout . 62 a yref the bottom of the ref erence ladder of the y -adc . this should be connected to ana- log g round (a gnd). 64 a cref+ the top of the ref erence ladder of the c-adc . this should be connected to refout . 73 a cref the bottom of the ref erence ladder of the c-adc . this should be connected to ana- log g round (a gnd). 74 a clevel an input to pro vide the dc le v el ref erence f or the c-adc . f or compatibility with bt829 board la y outs , the 30 k w divider resistors ma y be maintained. note: this pin should be left to oat f or ne w bt829a designs . 51 a n/c no connect. 46 a n/c no connect. 63, 68 a n/c no connect. 70 a n/c no connect. 69 a n/c no connect. i 2 c interface pins 19 i scl the i 2 c ser ial cloc k line . 18 i/o sd a the i 2 c ser ial data line . 14 i i2ccs the i 2 c chip select input (ttl compatib le). this pin selects one of tw o bt829a de vices in the same system. this pin is inter nally pulled to g round with an eff ectiv e 18 k w resistance . 15 i rst reset control input (ttl compatib le). a logical z ero f or a minim um of f our consecu- tiv e cloc k cycles resets the de vice to its def ault state . a logical z ero f or less than eight xt al cycles will lea v e the de vice in an undeter mined state .
bt829a/827a v ideostr eam ii decoders 8 f unctional d escription pin descriptions l829a_b video timing unit pins 82 o hreset hor iz ontal reset output (ttl compatib le). this signal indicates the beginning of a ne w line of video . this signal is 64 clkx1 cloc k cycles wide . the f alling edge of this output indicates the beginning of a ne w scan line of video . this pin ma y be de ned in pix els as opposed to clkx1 cycles . ref er to the hsfmt bit in the vtc register . note: the polar ity of this pin is prog r ammab le through the vpole register . 79 o vreset v er tical reset output (ttl compatib le). this signal indicates the beginning of a ne w eld of video . this signal is output coincident with the r ising edge of clkx1, and is nor mally six lines wide . the f alling edge of vreset indicates the beginning of a ne w eld of video . note: the polar ity of this pin is prog r ammab le through the vpole register . 83 o a ctive activ e video output (ttl compatib le). this pin can be prog r ammed to output the composite activ e or hor iz ontal activ e signal via the vtc register . it is a logical high dur ing the activ e/vie w ab le per iods of the video stream. the activ e region of the video stream is prog r ammab le . note: the polar ity of this pin is prog r ammab le through the vpole register . 94 o qclk quali ed cloc k output. this pin pro vides a r ising edge only dur ing v alid, activ e pix el data. this output is gener ated from clkx1 (or clkx2 in 8-bit mode), d v alid and, if prog r ammed, a ctive. the phase of qclk is in v er ted from the clkx1 (or clkx2) to ensure adequate setup and hold time with respect to the data outputs . qclk is not output dur ing control codes when using spi mode 2. 98 i oe output enab le control (ttl compatib le). all video timing unit output pins and all cloc k interf ace output pins contain v alid data f ollo wing the r ising edge of clkx2, after oe has been asser ted lo w . this function is asynchronous . the three-stated pins include: vd[15:0], hreset , vreset , a ctive, d v alid , cbfla g, field , qclk, clkx1, and clkx2. see the oes bits in the oform register to disab le subg roups of output pins . 78 o field odd/ev en field output (ttl compatib le). a high state on the field pin indicates that an odd eld is being digitiz ed. note: the polar ity of this pin is prog r ammab le through the vpole register . 89 o cbfla g cb data identi er (ttl compatib le). a high state on this pin indicates that the current chroma b yte contains cb chroma inf or mation. note: the polar ity of this pin is prog r ammab le through the vpole register . 2? o vd[15:8] digitiz ed video data outputs (ttl compatib le). vd[0] is the least signi cant bit of the b us in 16-bit mode . vd[8] is the least signi cant bit of the b us in 8-bit mode . the inf or mation is output with respect to clkx1 in 16-bit mode , and clkx2 in 8-bit mode . in mode 2, this por t is con gured to output control codes as w ell as data. when data is output in 8-bit mode using vd[15:8], vd[7:0] can be used as gener al pur pose i/o pins . see the p_io register . 22?9 i/o vd[7:0] 84 o d v alid data v alid output (ttl compatib le). this pin indicates when a v alid pix el is being output onto the data b us . the bt829a digitiz es video at eight times the subcarr ier r ate , and outputs scaled video . theref ore , there are more cloc ks than v alid data. d v alid indicates when v alid pix el data is being output. note: the polar ity of this pin is prog r ammab le through the vpole register . t ab le 2. pin descriptions gr ouped by pin function (2 of 4) pin # i/o pin name description
9 f unctional d escription pin descriptions l829a_b bt829a/827a v ideostr eam ii decoders 87 o ccv alid a logical lo w on this pin indicates that the cc fifo is half full (8 char acters). this pin ma y be disab led. this open dr ain output requires a pullup resistor f or proper oper a- tion. ho w e v er , if closed captioning is not implemented, this pin ma y be left uncon- nected. 91 i pwrdn a logical high on this pin puts the de vice into po w er-do wn mode . this is equiv alent to prog r amming clk_sleep high in the adc register . 86 o v a ctive v er tical blanking output (ttl compatib le). the f alling edge of v a ctive indicates the beginning of the activ e video lines in a eld. this occurs vdela y/2 lines after the r ising edge of vreset . the r ising edge of v a ctive indicates the end of activ e video lines and occurs a ctive_lines/2 lines after the f alling edge of v a ctive. v a ctive is output f ollo wing the r ising edge of clkx1. note: the polar ity of the pin is prog r ammab le through the vpole register . 85 i oepole a logical lo w on this pin allo ws the bt829a/827a to po w er up in the same manner as the bt829/827. a logical high on this pin, f ollo w ed b y a de vice reset will trist a te the video outputs , sync outputs and cloc k outputs . cloc k interface pins 12 a xt0i cloc k zero pins . a 28.64 mhz (8*fsc) fundamental (or third har monic) cr ystal can be tied directly to these pins , or a single-ended oscillator can be connected to xt0i. cmos le v el inputs m ust be used. this cloc k source is selected f or ntsc input sources . when the chip is con gured to decode p al b ut not ntsc (and theref ore only one cloc k source is needed), the 35.47 mhz source is connected to this por t (xt0). 13 a xt0o 16 a xt1i cloc k one pins . a 35.47 mhz (8*fsc) fundamental (or third har monic) cr ystal can be tied directly to these pins , or a single-ended oscillator can be connected to xt1i. cmos le v el inputs m ust be used. this cloc k source is selected f or p al input sources . if only ntsc or p al is being decoded, and theref ore only xt0i and xt0o are connected to a cr ystal, xt1i should be tied either high or lo w , and xt1o m ust be left oating. 17 a xt1o 97 o clkx1 1x cloc k output (ttl compatib le). the frequency of this cloc k is 4*fsc (14.31818 mhz f or ntsc or 17.73447 mhz f or p al). 99 o clkx2 2x cloc k output (ttl compatib le). the frequency of this cloc k is 8*fsc (28.63636 mhz f or ntsc , or 35.46895 mhz f or p al). 80 i numxt al cr ystal f or mat pin. this pin is set to indicate whether one or tw o cr ystals are present so that the bt829a can select xt1 or xt0 as the def ault in auto f or mat mode . a logi- cal z ero on this pin indicates one cr ystal is present. a logical one indicates tw o cr ys- tals are present. this pin is inter nally pulled do wn to g round with an eff ectiv e 18 k w resistance . t ab le 2. pin descriptions gr ouped by pin function (3 of 4) pin # i/o pin name description
bt829a/827a v ideostr eam ii decoders 10 f unctional d escription pin descriptions l829a_b jt a g pins 34 i tck t est cloc k (ttl compatib le). used to synchroniz e all jt a g test str uctures . when jt a g oper ations are not being perf or med, this pin m ust be dr iv en to a logical lo w . 36 i tms t est mode select (ttl compatib le). jt a g input pin whose tr ansitions dr iv e the jt a g state machine through its sequences . when jt a g oper ations are not being per- f or med, this pin m ust be left oating or tied high. 37 i tdi t est data input (ttl compatib le). jt a g pin used f or loading instr uction into the t ap controller or f or loading test v ector data f or boundar y-scan oper ation. when jt a g oper ations are not being perf or med, this pin m ust be left oating or tied high. 32 o tdo t est data output (ttl compatib le). jt a g pin used f or v er ifying test results of all jt a g sampling oper ations . this output pin is activ e f or cer tain jt a g oper ations and will be three-stated at all other times . 35 i trst t est reset (ttl compatib le). jt a g pin used to initializ e the jt a g controller . this pin is tied lo w f or nor mal de vice oper ation. when pulled high, the jt a g controller is ready f or de vice testing. p o wer and gr ound pins 1, 10, 20, 30, 38, 76, 88, 92, 96 p vdd +5 v p o w er supply f or digital circuitr y . all vdd pins m ust be connected together as close to the de vice as possib le . a 0.1 m f cer amic capacitor should be connected betw een each g roup of vdd pins and the g round plane as close to the de vice as possib le . 40, 44, 48, 60, 65, 72 p v aa +5 v , vpos +5 v p o w er supply f or analog circuitr y . all v aa pins and vpos m ust be connected together as close to the de vice as possib le . a 0.1 m f cer amic capacitor should be connected betw een each g roup of v aa pins and the g round plane as close to the de vice as possib le . 11, 21, 31, 33, 39, 77, 81, 90, 93, 95, 100 g gnd ground f or digital circuitr y . all gnd pins m ust be connected together as close to the de vice as possib le . 42, 47, 54, 56, 58, 61, 66, 71, 75 g a gnd , vneg ground f or analog circuitr y . all a gnd pins and vneg m ust be connected together as close to the de vice as possib le . i/o column legend: i = digital input o = digital output i/o = digital bidirectional a = analog g = ground p = p o w er t ab le 2. pin descriptions gr ouped by pin function (4 of 4) pin # i/o pin name description
11 f unctional d escription diff erences between bt829/827 and bt829a/827a l829a_b bt829a/827a v ideostr eam ii decoders diff erences between bt829/827 and bt829a/827a while both bt829/827 and bt829a/827a video decoders are pin and softw are compatible, please note the follo wing re gister dif ferences sho wn in t able 3 . t ab le 3. register diff erences register bits bt829/827 bt829a/827a comments 0x11 register (reser ved in bt829, wc_up in bt829a) [7:6] reser v ed majs compar ison point f or white cr ush [5:0] reser v ed upcnt a gc accum ulator idcode register [7:4] p ar t_id p ar t_id will re ect bt829a and BT827A codes [3:0] p ar t_rev p ar t_rev vtc register [2] reser v ed v alid fmt video timing control 0x1e register (reser ved in bt829, wc_dn in bt829a) [7] reser v ed ver ten impro v es v er tical loc king [6] reser v ed wc frame white cr ush control [5:0] reser v ed dncnt a gc accum ulator
bt829a/827a v ideostr eam ii decoders 12 f unctional d escription ultraloc k l829a_b ultraloc k the challeng e the line length (the interv al between the midpoints of the f alling edges of succeed- ing horizontal sync pulses) of analog video sources is not constant. f or a stable source such as a studio grade video source or test signal generators, this v ariation is v ery small: 2 ns. ho we v er , for an unstable source such as a vcr, laser disk player , or tv tuner , line length v ariation is as much as a fe w microseconds. digital display systems require a x ed number of pix els per line, despite these v ariations. the bt829a emplo ys a technique kno wn as ultralock to implement locking to the horizontal sync and the subcarrier of the incoming analog video sig- nal and generating the required number of pix els per line. operation principles of ultraloc k ultralock is based on sampling, using a x ed-frequenc y stable clock. because the video line length will v ary , the number of samples generated using a x ed-fre- quenc y sample clock will also v ary from line to line. if the number of generated samples per line is al w ays greater than the number of samples per line required by the particular video format, the number of acquired samples can be reduced to t the required number of pix els per line. the bt829a requires an 8*fsc (28.64 mhz for ntsc and 35.47 mhz for p al) crystal or oscillator input signal source. the 8*fsc clock signal, or clkx2, is di- vided do wn to clkx1 internally (14.32 mhz for ntsc and 17.73 mhz for p al). both clkx2 and clkx1 are made a v ailable to the system. ultralock operates at clkx1 although the input w a v eform is sampled at clkx2 then lo w-pass ltered and decimated to clkx1 sample rate. at a 4*fsc (clkx1) sample rate there are 910 pix els for ntsc and 1,135 pix els for p al/secam within a nominal line time interv al (63.5 m s for ntsc and 64 m s for p al/secam). f or square pix el ntsc and p al/secam formats there should only be 780 and 944 pix els per video line, respecti v ely . this is because the square pix el clock rates are slo wer than a 4*fsc clock rate: for e xample, 12.27 mhz for ntsc and 14.75 mhz for p al. ultralock accommodates line length v ariations from nominal in the incom- ing video by al w ays acquiring more samples (at an ef fecti v e 4*fsc rate) than are required by the particular video format. it then outputs the correct number of pix els per line. ultralock then interpolates the required number of pix els so that it maintains the stability of the original image, despite v ariation in the line length of the incoming analog w a v eform. the e xample illustrated in figure 3 sho ws three successi v e lines of video being decoded for square pix el ntsc output. the rst line is shorter than the nominal ntsc line time interv al of 63.5 m s. on this rst line, a line time of 63.2 m s sampled at 4*fsc (14.32 mhz) generates only 905 pix els. the second line matches the nominal line time of 63.5 m s and pro vides the e xpected 910 pix els. finally , the third line is too long at 63.8 m s within which 913 pix els are generated. in all three cases, ultralock outputs only 780 pix els.
13 f unctional d escription ultraloc k l829a_b bt829a/827a v ideostr eam ii decoders ultralock can be used to e xtract an y programmable number of pix els from the original video stream as long as the sum of the nominal pix el line length (910 for ntsc and 1,135 for p al/secam) and the w orst case line length v ariation from nominal in the acti v e re gion is greater than or equal to the required number of output pix els per line, i.e., no te: f or stable inputs, ultralock guarantees the time between the f alling edges of hreset only to within one pix el. ultralock does, ho we v er , guarantee the number of acti v e pix els in a line as long as the abo v e rela- tionship holds. figure 3. ultraloc k beha vior f or ntsc square pix el output analog waveform 63.2 m s 63.5 m s 63.8 m s 905 pixels 910 pixels 913 pixels line length pixels per line 780 pixels 780 pixels 780 pixels pixels sent to the fifo by ultralock p n o m p v a r + p d e s i r e d 3 where: p nom = nominal number of pix els per line at 4*fsc sample rate (910 for ntsc, 1,135 for pal/secam) p var = variation of pixel count from nominal at 4*fsc (can be a positive or negative number) p desired = desired number of output pixels per line
bt829a/827a v ideostr eam ii decoders 14 f unctional d escription composite video input formats l829a_b composite video input formats the bt829a supports se v eral composite video input formats. t able 4 sho ws the dif ferent video formats and some of the countries in which each format is used. the video decoder must be programmed appropriately for each of the compos- ite video input formats. t able 5 lists the re gister v alues that need to be programmed for each input format. t ab le 4. video input formats suppor ted b y the bt829a format lines fields f sc countr y ntsc-m 525 60 3.58 mhz u .s ., man y others ntsc-j apan (1) 525 60 3.58 mhz j apan p al-b 625 50 4.43 mhz man y p al-d 625 50 4.43 mhz china p al-g 625 50 4.43 mhz man y p al-h 625 50 4.43 mhz belgium p al-i 625 50 4.43 mhz great br itain, others p al-m 525 60 4.43 mhz br azil p al-n 625 50 4.43 mhz p ar agua y , ur ugua y p al-n combi- nation 625 50 3.58 mhz argentina secam 625 50 4.406 mhz 4.250 mhz easter n europe , f r ance , middle east notes: (1). ntsc-japan has 0 ire setup.
15 f unctional d escription composite video input formats l829a_b bt829a/827a v ideostr eam ii decoders t ab le 5. register v alues f or video input formats register bit ntsc-m ntsc-japan p al-b, d , g, h, i p al-m p al-n p al-n combination secam iform (0x01) xtsel 4:3 01 01 10 01 10 01 10 forma t 2:0 001 010 011 100 101 111 110 cropping: hdela y , vdela y , v a ctive, cr op 7:0 in all 5 regis- ters set to desired cropping v alues in registers set to ntsc-m square pix el v alues set to desired cropping v alues in registers set to ntsc-m square pix el v al- ues set to p al-b , d , g, h, i square pix el v al- ues set to p al-b , d , g, h, i ccir v alues set to p al-b , d , g, h, i square pix el v al- ues hscale (0x08, 0x09) 15:0 0x02aa 0x02aa 0x033c 0x02a c 0x033c 0x00f8 0x033c adela y (0x18) 7:0 0x68 0x68 0x7f 0x68 0x7f 0x7f 0x7f bdela y (0x19) 7:0 0x5d 0x5d 0x72 0x5d 0x72 0x72 0xa0
bt829a/827a v ideostr eam ii decoders 16 f unctional d escription y/c separation and chr oma demodulation l829a_b y/c separation and chr oma demodulation y/c separation and chroma decoding are handled as sho wn in figure 4 . bandpass and notch lters are implemented to separate the composite video stream. figure 5 displays the lter responses. the optional chroma comb lter is implemented in the v ertical scaling block. see the v ideo scaling, cropping, and t emporal deci- mation section in this chapter . figure 4. y/c separation and chr oma demodulation f or composite video notch filter band-p ass filter lo w-p ass filter lo w-p ass filter sin cos y u v composite figure 5. y/c separation filter responses ntsc p al/secam ntsc p al/secam luma notch filter f requency responses f or ntsc and p al/secam chroma band p ass filter f requency responses f or ntsc and p al/secam
17 f unctional d escription y/c separation and chr oma demodulation l829a_b bt829a/827a v ideostr eam ii decoders figure 6 schematically describes the ltering and scaling operations. in addition to the y/c separation and chroma demodulation illustrated in figure 4 , the bt829a also supports chrominance comb ltering as an optional l- tering stage after chroma demodulation. the chroma demodulation generates baseband i and q (ntsc) or u and v (p al/secam) color dif ference signals. f or s-v ideo operation, the digitized luma data bypasses the y/c separation block completely , and the digitized chrominance is passed directly to the chroma demodulator . f or monochrome operation, the y/c separation block is also bypassed, and the saturation re gisters (sa t_u and sa t_v) are set to zero. figure 6. filtering and scaling note: z? refers to a pixel delay in the horizontal direction, and a line delay in the vertical direction. the coefficients are determined by ultralock and the scaling algorithm. c h r o m i n a n c e 1 2 - - - 1 2 - - - z 1 + = l u m i n a n c e c d z 1 + = v er tical scaler l u m i n a n c e a b z 1 c z 2 d z 3 e z 4 f z 5 + + + + + = c h r o m i n a n c e g h z 1 + = hor iz ontal scaler 6-t ap , 32-phase inter polation on-chip memor y and hor iz ontal scaling 2-t ap , 32-phase inter polation on-chip memor y and and hor iz ontal scaling chroma comb lo w-p ass filter y y c c optional hor iz ontal v er tical scaling luma comb (chroma comb) 3 mhz 1 4 - - - 1 2 z 1 1 z 2 + + ( ) = 1 8 - - - 1 3 z 1 3 z 2 1 z 3 + + + ( ) = 1 16 - - - - - - 1 4 z 1 6 z 2 4 z 3 z 4 + + + + ( ) = v er tical filter options v er tical scaling v er tical filter ing l u m i n a n c e 1 2 - - - 1 z 1 + ( ) =
bt829a/827a v ideostr eam ii decoders 18 f unctional d escription video scaling, cr opping, and t emporal decimation l829a_b video scaling, cr opping, and t emporal decimation the bt829a pro vides three mechanisms to reduce the amount of video pix el data in its output stream: do wn-scaling, cropping, and temporal decimation. all three can be controlled independently . horizontal and v er tical scaling the bt829a pro vides independent and arbitrary horizontal and v ertical do wn-scal- ing. the maximum scaling ratio is 16:1 in both x and y dimensions. the maxi- mum v ertical scaling ratio is reduced from 16:1 when using frames to 8:1 when using elds. the dif ferent methods utilized for scaling luminance and chromi- nance are described in the follo wing sections. luminance scaling the rst stage in horizontal luminance scaling is an optional pre- lter which pro- vides the capability to reduce anti-aliasing artif acts. it is generally desirable to lim- it the bandwidth of the luminance spectrum prior to performing horizontal scaling because the scaling of high-frequenc y components may create image artif acts in the resized image. the optional lo w-pass lters sho wn in figure 7 reduce the hor - izontal high-frequenc y spectrum in the luminance signal. figure 8 and figure 9 sho w the combined results of the optional lo w-pass lters, and the luma notch and 2x o v ersampling lter . figure 7. optional horizontal luma lo w-p ass filter responses ntsc p al/secam icon qcif cif icon qcif cif
19 f unctional d escription video scaling, cr opping, and t emporal decimation l829a_b bt829a/827a v ideostr eam ii decoders the bt829a implements horizontal scaling through poly-phase interpolation. the bt829a uses 32 dif ferent phases to accurately interpolate the v alue of a pix el. this pro vides an ef fecti v e pix el jitter of less than 6 ns. in simple pix el- and line-dropping algorithms, non-inte ger scaling ratios intro- duce a step function in the video signal that ef fecti v ely introduces high-frequenc y spectral components. poly-phase interpolation accurately interpolates to the cor - rect pix el and line position pro viding more accurate information. this results in more aesthetically pleasing video as well as higher compression ratios in band- width limited applications. f or v ertical scaling, the bt829a uses a line store to implement four dif ferent l- tering options. the lter characteristics are sho wn in figure 10 . the bt829a pro- vides up to 5-tap ltering to ensure remo v al of aliasing artif acts. figure 11 sho ws the combined responses of the luma notch and 2x o v ersampling lters. figure 8. combined luma notc h, 2x over sampling and optional lo w-p ass filter response (ntsc) icon qcif cif icon qcif cif p ass band full spectr um figure 9. combined luma notc h, 2x over sampling and optional lo w-p ass filter response (p al/secam) icon qcif cif icon qcif cif p ass band full spectr um
bt829a/827a v ideostr eam ii decoders 20 f unctional d escription video scaling, cr opping, and t emporal decimation l829a_b figure 10. frequenc y responses f or the four optional v er tical luma lo w-p ass filter s 2-tap 3-tap 4-tap 5-tap figure 11. combined luma notc h and 2x over sampling filter response ntsc p al/secam
21 f unctional d escription video scaling, cr opping, and t emporal decimation l829a_b bt829a/827a v ideostr eam ii decoders p eaking the bt829a enables four dif ferent peaking le v els by programming the peak bit and hfil t bits in the scloop re gister . the lters are sho wn in figures 12 and 13 . figure 12. p eaking filter s hfil t = 00 hfil t = 11 hfil t = 10 hfil t = 01 hfil t = 00 hfil t = 10 hfil t = 11 hfil t = 01 enhanced resolution of p assband
bt829a/827a v ideostr eam ii decoders 22 f unctional d escription video scaling, cr opping, and t emporal decimation l829a_b the number of taps in the v ertical lter is set by the vtc re gister . the user may select 2, 3, 4, or 5 taps. the number of taps must be chosen in conjunction with the horizontal scale f actor to ensure that the needed data can t in the internal fifo (see the vfil t bits in the vtc re gister for limitations). as the scaling ratio is in- creased, the number of taps a v ailable for v ertical scaling is increased. in addition to lo w-pass ltering, v ertical interpolation is also emplo yed to minimize artif acts when scaling to non-inte ger scaling ratios. the BT827A emplo ys line dropping for v ertical scaling. figure 13. luma p eaking filter s with 2x over sampling filter and luma notc h hfil t = 00 hfil t = 11 hfil t = 01 hfil t = 10 hfil t = 00 hfil t = 10 hfil t = 11 hfil t = 01 enhanced resolution of p assband
23 f unctional d escription video scaling, cr opping, and t emporal decimation l829a_b bt829a/827a v ideostr eam ii decoders chr ominance scaling a 2-tap, 32-phase interpolation lter is used for horizontal scaling of chrominance. v ertical scaling of chrominance is implemented through chrominance comb lter - ing using a line store, follo wed by simple decimation or line dropping. scaling register s horizontal scaling ratio register (hscale) hscale is programmed with the horizontal scaling ratio. when outputting unscaled video (in ntsc), the bt829a will produce 910 pix els per line. this corresponds to the pix el rate at f clkx1 (4*fsc). this re gister is the control for scaling the video to the desired size. f or e x- ample, square pix el ntsc requires 780 samples per line, while ccir601 requires 858 samples per line. hscale_hi and hscale_lo are tw o 8-bit re gisters that, when concatenated, form the 16-bit hscale re gister . the method belo w uses pix el ratios to determine the scaling ratio. the follo w- ing formula should be used to determine the scaling ratio to be entered into the 16-bit re gister: f or e xample, to scale p al/secam input to square pix el qcif , the total number of horizontal pix els is 236: an alternati v e method for determining the hscale v alue uses the ratio of the scaled acti v e re gion to the unscaled acti v e re gion as sho wn belo w: in this equation, the ha ctive v alue cannot be cropped; it represents the total ac- ti v e re gion of the video line. this equation produces roughly the same result as us- ing the full line length ratio sho wn in the rst e xample. ho we v er , due to truncation, the hscale v alues determined using the acti v e pix el ratio will be slightly dif fer - ent than those obtained using the total line length pix el ratio. the v alues in t able 6 were calculated using the full line length ratio. ntsc: hscale = [ ( 910/p desired ) ?1] * 4096 pal/secam: hscale = [ ( 1135/p desired ) ?1] * 4096 where: p desired = desired number of pixels per line of video, includ- ing active, sync and blanking. hscale = [ ( 1135/236 ) ?1 ] * 4096 = 15602 = 0x3cf2 ntsc: hscale = [ (754 / hactive) ?1] * 4096 pal/secam: hscale = [ (922 / hactive) ?1] * 4096 where: hactive = desired number of pixels per line of video, not in- cluding sync or blanking.
bt829a/827a v ideostr eam ii decoders 24 f unctional d escription video scaling, cr opping, and t emporal decimation l829a_b v er tical scaling ratio register (vscale) vscale is programmed with the v er - tical scaling ratio. it de nes the number of v ertical lines output by the bt829a. the follo wing formula should be used to determine the v alue to be entered into this 13-bit re gister . the loaded v alue is a tw o s-complement, ne g ati v e v alue. f or e xample, to scale p al/secam input to square pix el qcif , the total number of v ertical lines for p al square pix el is 156 (see t able 6 ). t ab le 6. scaling ratios f or p opular formats using frequenc y v alues scaling ratio format t otal resolution (inc luding sync and b lanking inter v al) output resolution (active pix els) hscale register v alues vscale register v alues use both fields single field full resolution 1:1 ntsc sq pix el ntsc ccir601 p al ccir601 p al sq pix el 780 x 525 858 x 525 864 x 625 944 x 625 640 x 480 720 x 480 720 x 576 768 x 576 0x02a c 0x00f8 0x0504 0x033c 0x0000 0x0000 0x0000 0x0000 n/a n/a n/a n/a cif 2:1 ntsc sq pix el ntsc ccir601 p al ccir601 p al sq pix el 390 x 262 429 x 262 432 x 312 472 x 312 320 x 240 360 x 240 360 x 288 384 x 288 0x1555 0x11f0 0x1a09 0x1679 0x1e00 0x1e00 0x1e00 0x1e00 0x0000 0x0000 0x0000 0x0000 qcif 4:1 ntsc sq pix el ntsc ccir601 p al ccir601 p al sq pix el 195 x 131 214 x 131 216 x 156 236 x 156 160 x 120 180 x 120 180 x 144 192 x 144 0x3aaa 0x3409 0x4412 0x3cf2 0x1a00 0x1a00 0x1a00 0x1a00 0x1e00 0x1e00 0x1e00 0x1e00 icon 8:1 ntsc sq pix el ntsc ccir601 p al ccir601 p al sq pix el 97 x 65 107 x 65 108 x 78 118 x 78 80 x 60 90 x 60 90 x 72 96 x 72 0x861a 0x7813 0x9825 0x89e5 0x1200 0x1200 0x1200 0x1200 0x1a00 0x1a00 0x1a00 0x1a00 notes: 1. p al-m?scale and vscale register v alues should be the same f or ntsc . 2. p al-n combination?scale register v alues should be the same as f or ccir resolution ntsc . vscale reg- ister v alues should be the same as f or ccir resolution p al. 3. secam?scale and vscale register v alues should be the same as f or p al. vscale = ( 0x10000 ?{ [ ( scaling_ratio ) ?1] * 512 } ) & 0x1fff vscale = ( 0x10000 ?{ [ ( 4/1 ) ? ] * 512 } ) & 0x1fff = 0x1a00
25 f unctional d escription video scaling, cr opping, and t emporal decimation l829a_b bt829a/827a v ideostr eam ii decoders note that only the 13 least signi cant bits of the vscale v alue are used. the v e lsbs of vscale_hi and the 8-bit vscale_lo re gister form the 13-bit vs- cale re gister . the three msbs of vscale_hi are used to control other func- tions. the user must tak e care not to alter the v alues of the three most signi cant bits when writing a v ertical scaling v alue. the follo wing c-code fragment illus- trates changing the v ertical scaling v alue: #define byte unsigned char #define word unsigned int #define vscale_hi 0x13 #define vscale_lo 0x14 byte readfrombt829a( byte regaddress ); void writetobt829a( byte regaddress, byte regvalue ); void setbt829avscaling( word vscale ) { byte oldvscalemsbyte, newvscalemsbyte; /* get existing vscalemsbyte value from */ /* bt829a vscale_hi register */ oldvscalemsbyte = readfrombt829a( vscale_hi ); /* create a new vscalemsbyte, preserving top 3 bits */ newvscalemsbyte = (oldvscalemsbyte & 0xe0) | (vscale >> 8); /* send the new vscalemsbyte to the vscale_hi reg */ writetobt829a( vscale_hi, newvscalemsbyte ); /* send the new vscalelsbyte to the vscale_lo reg */ writetobt829a( vscale_lo, (byte) vscale ); } if your tar get machine has suf cient memory to statically store the scaling v al- ues locally , the read operation can be eliminated. on v ertical scaling (when scaling belo w cif resolution) it may be useful to use a single eld as opposed to using both elds. using a single eld will ensure there are no inter - eld motion artif acts on the scaled output. when performing single eld scaling, the v ertical scaling ratio will be twice as lar ge as when scaling with both elds. f or e xample, cif scaling from one eld does not require an y v ertical scaling, b ut when scaling from both elds, the scaling ratio is 50%. also, the non-interlaced bit should be reset when scaling from a single eld (int = 0 in the vscale_hi re gister). t able 6 lists scaling ratios for v arious video formats, and the re gister v alues required. where: & = bitwise and | = bitwise or >> = bit shift, msb to lsb
bt829a/827a v ideostr eam ii decoders 26 f unctional d escription video scaling, cr opping, and t emporal decimation l829a_b ima g e cr opping cropping enables the user to output an y subsection of the video image. the a c- tive ag can be programmed to start and stop at an y position on the video frame as sho wn in figure 14 . the start of the acti v e area in the v ertical direction is refer - enced to vreset (be ginning of a ne w eld). in the horizontal direction it is ref- erenced to hreset (be ginning of a ne w line). the dimensions of the acti v e video re gion are de ned by hdela y , ha ctive, vdela y , and v a ctive. all four re gisters are 10-bit v alues. the tw o msbs of each re gister are contained in the cr op re gister , while the lo wer eight bits are in the respecti v e hdela y_lo, ha ctive_lo, vdela y_lo, and v a ctive_lo re gisters. the v ertical and horizontal delay v alues determine the position of the cropped image within a frame while the horizontal and v ertical acti v e v alues set the pix el dimensions of the cropped image as illustrated in figure 14 .
27 f unctional d escription video scaling, cr opping, and t emporal decimation l829a_b bt829a/827a v ideostr eam ii decoders figure 14. eff ect of the cr opping and active register s rising edge of vreset falling edge of hreset video frame hactive hdelay vdelay vactive video frame hactive hdelay vdelay vactive cropped image cropped image scaled to 1/2 size
bt829a/827a v ideostr eam ii decoders 28 f unctional d escription video scaling, cr opping, and t emporal decimation l829a_b cr opping register s horizontal dela y register (hdela y) hdela y is programmed with the delay between the f alling edge of hreset and the rising edge of a ctive. the count is programmed with respect to the scaled frequenc y clock. note that hdela y should al w ays be an e v en number . horizontal active register (ha ctive) ha ctive is programmed with the actual number of acti v e pix els per line of video. this is equi v alent to the number of scaled pix els that the bt829a should output on a line. f or e xample, if this re gister con- tained 90, and hscale w as programmed to do wn-scale by 4:1, then 90 acti v e pix els w ould be output. the 90 pix els w ould be a 4:1 scaled image of the 360 pix els (at clkx1) starting at count hdela y . ha ctive is restricted in the follo wing manner: ha ctive + hdela y t otal number of scaled pix els. f or e xample, in the ntsc square pix el format, there is a total of 780 pix els, in- cluding blanking, sync and acti v e re gions. therefore: ha ctive + hdela y 780. when scaled by 2:1 for cif , the total number of acti v e pix els is 390. therefore: ha ctive +hdela y 390. the hdela y re gister is programmed with the number of scaled pix els be- tween hreset and the rst acti v e pix el. because the front porch is de ned as the distance between the last acti v e pix el and the ne xt horizontal sync, the video line can be considered in three components: hdela y , ha ctive and the front porch. figure 15 illustrates the video signal re gions. when cropping is not implemented, the number of clocks at the 4x sample rate (the clkx1 rate) in each of these re gions is as follo ws: figure 15. regions of the video signal hdela y ha ctive f ront p orch clkx1 fr ont p or c h clkx1 hdela y clkx1 ha ctive clkx1 t otal ntsc 21 135 754 910 p al/secam 27 186 922 1135
29 f unctional d escription video scaling, cr opping, and t emporal decimation l829a_b bt829a/827a v ideostr eam ii decoders the v alue for hdela y is calculated using the follo wing formula: hdela y = [(clkx1_hdela y / clkx1_ha ctive) * ha ctive] & 0x3fe clkx1_hdela y and clkx1_ha ctive are constant v alues, so the equation becomes: ntsc: hdela y = [(135 / 754) * ha ctive] & 0x3fe p al/secam: hdela y = [(186 / 922) * ha ctive] & 0x3fe in this equation, the ha ctive v alue cannot be cropped. v er tical dela y register (vdela y) vdela y is programmed with the delay be- tween the rising edge of vreset and the start of acti v e video lines. it determines ho w man y lines to skip before initiating the a ctive signal. it is programmed with the number of lines to skip at the be ginning of a frame. v er tical active register (v a ctive) v a ctive is programmed with the number of lines used in the v ertical scaling process. the actual number of v ertical lines out- put from the bt829a is equal to this re gister times the v ertical scaling ratio. if vs- cale is set to 0x1a00 (4:1), then the actual number of lines output is v a ctive/4. if vscale is set to 0x0000 (1:1), then v a ctive contains the actu- al number of v ertical lines output. no te: it is important to note the dif ference between the implementation of the horizontal re gisters (hscale, hdela y , and ha ctive) and the v erti- cal re gisters (vscale, vdela y , and v a ctive). horizontally , hde- la y and ha ctive are programmed with respect to the scaled pix els de ned by hscale. v ertically , vdela y and v a ctive are pro- grammed with respect to the number of lines before scaling (before vs- cale is applied). t emporal decimation t emporal decimation pro vides a solution for video synchronization during periods when full frame rate cannot be supported due to bandwidth and system restrictions. f or e xample, when capturing li v e video for storage, system limitations such as hard disk transfer rates or system b us bandwidth may limit the frame capture rate. if these restrictions limit the frame rate to 15 frames per second, the bt829a s time scaling operation will enable the system to capture e v ery other frame instead of al- lo wing the hard disk timing restrictions to dictate which frame to capture. this maintains an e v en distrib ution of captured frames and alle viates the ?erk y?ef fects caused by systems that simply b urst in data when the bandwidth becomes a v ail- able. the bt829a pro vides temporal decimation on either a eld or frame basis. the temporal decimation re gister (tdec) is loaded with a v alue from 1 to 60 (ntsc) or 1 to 50 (p al/secam). this v alue is the number of elds or frames skipped by the chip during a sequence of 60 for ntsc or 50 for p al/secam. skipped elds and frames are considered inacti v e, which is indicated by the a ctive pin remain- ing lo w . consequently if qclk is programmed to depend on a ctive, qclk w ould become inacti v e as well.
bt829a/827a v ideostr eam ii decoders 30 f unctional d escription video scaling, cr opping, and t emporal decimation l829a_b examples: when changing the programming in the temporal decimation re gister , 0x00 should be loaded rst, and then the decimation v alue. this will ensure that the dec- imation counter is reset to zero. if zero is not rst loaded, the decimation may start on an y eld or frame in the sequence of 60 (or 50 for p al/secam). on po wer -up, this preload is not necessary because the counter is internally reset. when decimating elds, the fld align bit in the tdec re gister can be pro- grammed to choose whether the decimation starts with an odd eld or an e v en eld. if the fld align bit is set to logical zero, the rst eld that is dropped dur - ing the decimation process will be an odd eld. con v ersely , setting the fld align bit to logical one causes the e v en eld to be dropped rst in the dec- imation process. tdec = 0x02 decimation is performed by frames. two frames are skipped per 60 frames of video, assuming ntsc decoding. frames 1?9 are output normally , then a c- tive remains lo w for one frame. frames 30?9 are then output follo wed by another frame of in- acti v e video. tdec = 0x9e decimation is performed by fields. thirty fields are output per 60 fields of video, assuming ntsc decoding. this v alue outputs e v ery other eld (e v ery odd eld) of video starting with eld one in frame one. tdec = 0x01 decimation is performed by frames. one frame is skipped per 50 frames of video, assuming pal/secam decoding. tdec = 0x00 decimation is not performed. full frame rate video is output by the bt829a.
31 f unctional d escription video adjustments l829a_b bt829a/827a v ideostr eam ii decoders video adjustments the bt829a pro vides programmable hue, contrast, saturation, and brightness. the hue adjust register (hue) the hue adjust re gister is used to of fset the hue of the decoded signal. in ntsc, the hue of the video signal is de ned as the phase of the subcarrier with reference to the b urst. the v alue programmed in this re gister is added or subtracted from the phase of the subcarrier , which ef fecti v ely changes the hue of the video. the hue can be shifted by plus or minus 90 de grees. because of the nature of p al/secam encoding, hue adjustments cannot be made when decoding p al/secam. the contrast adjust register (contrast) the contrast adjust re gister (also called the luma g ain) pro vides the ability to change the contrast from approximately 0 percent to 200 percent of the original v alue. the decoded luma v alue is multiplied by the 9-bit coef cient loaded into this re gister . the saturation adjust register s (sa t_u , sa t_v) the saturation adjust re gisters are additional color adjustment re gisters. it is a multiplicati v e g ain of the u and v signals. the v alue programmed in these re gis- ters are the coef cients for the multiplication. the saturation range is from approx- imately 0 percent to 200 percent of the original v alue. the brightness register (bright) the brightness re gister is simply an of fset for the decoded luma v alue. the pro- grammed v alue is added or subtracted from the original luma v alue which changes the brightness of the video output. the luma output is in the range of 0 to 255. brightness adjustment can be made o v er a range of ?28 to +127.
bt829a/827a v ideostr eam ii decoders 32 f unctional d escription bt829a vbi data output interface l829a_b bt829a vbi data output interface intr oduction a frame of video is composed of 525 lines for nstc and 625 for p al/secam. figure 16 illustrates an ntsc video frame in which there are a number of distinct re gions. the video image or picture data is contained in the odd and even elds within lines 21 to 262 and lines 283 to 525, respecti v ely . each eld of video also contains a re gion for v ertical synchronization (lines 1 through 9 and 263 through 272) as well as a re gion which can contain non-video ancillary data (lines 10 through 20 and 273 through 282). w e will refer to these re gions which are between the v ertical synchronization re gion and the video picture re gion as the v ertical blanking interv al or vbi portion of the video signal. over vie w in the def ault con guration of the bt829a, the vbi re gion of the video signal is treated the same w ay as the video image re gion of the signal. the bt829a will de- code this signal as if it w as video, i.e., it will digitize at 8xfsc, decimate/ lter to a 4xfsc sample stream, color separate to deri v e luma and chroma component infor - mation, and interpolate for video synchronization and horizontal scaling. this pro- cess is sho wn in figure 17 . figure 16. regions of the video frame lines 1? lines 10?0 lines 21?62 lines 263?72 lines 273?82 lines 283?25 v er tical blanking inter v al video image region v er tical blanking inter v al video image region odd field ev en field v er tical synchronization region v er tical synchronization region figure 17. bt829a ycrcb 4:2:2 data p ath decimation filter y/c separ ation filter inter polation filter adc composite analog ycrcb 4:2:2 8xfsc 4xfsc
33 f unctional d escription bt829a vbi data output interface l829a_b bt829a/827a v ideostr eam ii decoders the bt829a can be con gured in a mode kno wn as vbi data pass-through to enable capture of the vbi re gion ancillary data for later processing by softw are. in this mode the vbi re gion of the video signal is processed as follo ws: the analog composite video signal is digitized at 8*fsc (28.63636 mhz for ntsc and 35.46895 mhz for p al/secam). this 8-bit v alue repre- sents a number range from the bottom of sync tip to peak of the compos- ite video signal. the 8-bit data stream bypasses the decimation lter , y/c separation l- ters, and the interpolation lter (see figure 18 ). the bt829a pro vides the option to pack the 8*fsc data stream into a 2-byte-wide stream at 4*fsc before outputting it to the vd[15:0] data pins, or it can simply be output as an 8-bit 8*fsc data stream on pins vd[15:8]. in the pack ed format, the rst byte of each pair on a 4*fsc clock c ycle is mapped to vd[15:8] and the second byte to vd[7:0] with vd[7] and vd[15] being the msbs. the bt829a uses the same 16-pin data port for vbi data and ycrcb 4:2:2 image data. the byte pair order - ing is programmable. the vbi datastream is not pipeline delayed to match the ycrcb 4:2:2 im- age output data with respect to horizontal timing (i.e. v alid vbi data will be output earlier than ycrcb 4:2:2 relati v e to the bt829a hreset sig- nal). a lar ger number of pix els per line are generated in vbi output mode than in ycrcb 4:2:2 output mode. the do wnstream video processor must be capable of dealing with a v arying number of pix els per line in order to capture vbi data as well as ycrcb 4:2:2 data from the same frame. the follo wing pins may be used to implement this solution: vd[15:0], v a ctive, ha ctive, d v alid, vreset , hreset , clkx1, clkx2, qclk. this should allo w the do wnstream video processor to load the vbi data and the ycrcb 4:2:2 data correctly . because the 8*fsc data stream does not pass through the interpolation l- ter , the sample stream is not lock ed/synchronized to the horizontal sync timing. the only implication of this is that the sample locations on each line are not correlated v ertically . figure 18. bt829a vbi data p ath decimation filter y/c separ ation filter inter polation filter adc composite analog vbi data 8xfsc 4xfsc p ac k decimation filter y/c separ ation filter inter polation filter adc composite analog vbi data 8xfsc 8 16 8
bt829a/827a v ideost r eam ii decoders 34 f unctional d escription bt829 a vbi data output interface l829a_b functional description there are three modes of operation for the bt829 a vbi data pass-through feature: 1 . vbi data p ass-through disabled . this is the de f ault mode of operation for the bt829a during which the d e vice decodes composite video and generates a ycrcb 4:2:2 data stream. 2 . vbi line output mode . the d e vice outputs unltered 8*fsc data only during the v ertical inter v al which is de ned by th e v a ctive output sig- nal pr o vided by the bt829a. data is output between the trailing edge of th e vreset signal and the leading edge o f v a ctive . whe n v a ctive is high, the bt829a is outputting standar d ycrcb 4:2:2 data . this mode of operation is intended to be used to enable capture o f vbi lines contain- ing ancillary data in addition to processing norma l ycrcb 4:2:2 video image data. 3 . vbi frame output mode. in this mode the bt829a treats e v ery line in the video signal as if it were a v ertical inter v al line and outputs only the un ltered 8*fsc data on e v ery line (i.e., it does not output a n y image data) . this mode of operation is designed for use in still-frame cap- ture/processing applications. vbi line output mode th e vbi line output mode is enabled via th e vbien bit in th e vtc r e gister (0x1b) . when enabled, th e vbi data is output during th e vbi act i v e period . the vbi horizontal act i v e period is dened as the inter v al between consecut i v e bt829 a hreset signals. speci call y , it starts at a point one clkx1 inter v al after the trailing edge of the rst hreset and ends with the leading edge of the foll o w- in g hreset . this inter v al is coincident with the h a ctive signal as indicated in figur e 19 . d v alid is always at a logical one durin g vbi . also, qclk is operating con- tinuously at clkx1 or clkx2 rate durin g vbi . v ali d vbi data is a v ailable one clkx1 (or qclk) inter v al after the trailing edge of hreset . when the bt829a is congured i n vbi line output mode, it is generating i n v alid data outside of the vbi horizontal act i v e period. in standar d ycrcb output mode, the horizontal ac- t i v e period starts at a time point delayed from the leading edge of hreset as de- ned by the v alue programmed in the hdel a y r e giste r . figure 19 . vbi line output mod e timing hreset h a ctive vd[15:0] vbi data
35 f unctional d escription bt829a vbi data output interface l829a_b bt829a/827a v ideostr eam ii decoders the vbi data sample stream which is output during the vbi horizontal acti v e period represents an 8*fsc sampled v ersion of the analog video signal starting in the vicinity of the sub-carrier b urst and ending after the leading edge of the hori- zontal synchronization pulse as illustrated in figure 20 . the number of vbi data samples generated on each line may v ary depending on the stability of the analog composite video signal input to the bt829a. the bt829a will generate 845 16-bit vbi data w ords for ntsc and 1070 16-bit vbi data w ords for p al/secam on each vbi line at a clkx1 rate assuming a nominal or ideal video input signal (i.e., the analog video signal has a stable horizontal time base). this is also equi v alent to 1690 8-bit vbi data samples for ntsc and 2140 8-bit vbi data samples for p al/secam. these v alues can de viate from the nominal depending on the actual line length of the analog video signal. the vbi v ertical acti v e period is de ned as the period between the trailing edge of the bt829a vreset signal and the leading edge of v a ctive. note that the e xtent of the vbi v ertical acti v e re gion can be controlled by setting dif ferent v alues in the vdela y re gister . this pro vides the e xibility to con gure the vbi v ertical acti v e re gion as an y group of consecuti v e lines starting with line 10 and e xtending to the line number set by the equi v alent line count v alue in the vdela y re gister (i.e., the vbi v ertical acti v e re gion can be e xtended into the video image re gion of the video signal). the vbi horizontal acti v e period starts with the trailing edge of an hreset ; therefore, if a rising edge of vreset occurs after the horizontal acti v e period has already started, the vbi acti v e period starts on the follo wing line. the ha ctive pin is held at a logical one during the vbi horizontal acti v e period. d v alid is held high during both the vbi horizontal acti v e and horizontal inacti v e periods (i.e., it is held high during the whole vbi scan line.) these relationships are illustrated in figure 21 . figure 20. vbi sample region extent of analog signal captured in vbi samples
bt829a/827a v ideostr eam ii decoders 36 f unctional d escription bt829a vbi data output interface l829a_b figure 21. location of vbi data vreset hreset ha ctive v a ctive d v alid vd[15:0] vreset hreset ha ctive v a ctive d v alid vd[15:0] vbi data vbi data vbi data vbi data ycrcb data ycrcb data vbi activ e region vbi activ e region ev en field odd field in v alid data in v alid data vbi data vbi data
37 f unctional d escription bt829a vbi data output interface l829a_b bt829a/827a v ideostr eam ii decoders the bt829a can pro vide vbi data in all the pix el port output con gurations (i.e., 16-bit spi, 8-bit spi, and bytestream modes). the range of the vbi data can be controlled with the range bit in the oform re gister (0x12). it is nec- essary to limit the range of vbi data for bytestream output mode. there must be a video signal present on the bt829a analog input as de ned by the status of the vpres bit in the st a tus re gister in order for the bt829a to gen- erate vbi data. if the status of the vpres bit re ects no analog input, then the bt829a generates ycrcb data to create a at blue eld image. the order in which the vbi data is presented on the output pins is programma- ble. setting the vbifmt bit in the vtc re gister to a logical zero places the nth data sample on vd[15:8] and the nth+1 sample on vd[7:0]. setting vbifmt to a log- ical one re v erses the abo v e. similarly , in bytestream and 8-bit output modes, setting vbifmt = 0 generates a vbi sample stream with an ordering sequence of n+1, n, n+3, n+2, n+5, n+4, etc. setting vbifmt = 1 for bytestream/8-bit out- put generates an n, n+1, n+2, n+3, etc. sequence as sho wn in figure 22 . a video processor/controller should be able to do the follo wing to capture vbi data output by the bt829a: k eep track of the line count in order to select a limited number of speci c lines for processing of vbi data. handle data type transitioning on the y from the v ertical interv al to the acti v e video image re gion. f or e xample, during the v ertical interv al with vbi data pass-through enabled, it must grab e v ery byte pair while ha ctive is high using the 4*fsc clock or qclk. ho we v er , when the data stream transitions into ycrcb 4:2:2 data mode with v a ctive going high, the video processor must interpret the d v alid signal (or use qclk for the data load clock) from the bt829a for pix el quali cation and use only v alid pix el c ycles to load image data (def ault bt829a operation). handle a lar ge and v arying number of horizontal pix els per line in the vbi re gion as compared to the acti v e image re gion. figure 22. vbi sample or dering vd[15:8] vd[7:0] clkx1 vd[15:8] clkx2 n n+2 n+1 n+3 n n+2 n+1 n+3 16-bit spi mode (vbifmt = 0) 8-bit spi mode (vbifmt = 1)
bt829a/827a v ideostr eam ii decoders 38 f unctional d escription bt829a vbi data output interface l829a_b vbi frame output mode in vbi frame output mode, the bt829a is generating vbi data all the time (i.e., there is no vbi acti v e interv al). in essence, the bt829a is acting as an adc con- tinuously sampling the entire video signal at 8*fsc. the bt829a generates hreset , vreset and field timing signals in addition to the vbi data, b ut the d v alid, ha ctive, and v a ctive signals are all held high during vbi frame output operation. the beha vior of the hreset , vreset , and field timing sig- nals is the same as normal ycrcb 4:2:2 output operation. the hreset , vreset , and field timing signals can be used by the video processor to detect the be gin- ning of a video frame/ eld, at which point it can start to capture a full frame/ eld of vbi data. the number of vbi data samples generated on each line may v ary depending on the stability of the analog composite video signal input to the bt829a. the bt829a will generate 910 16-bit vbi data w ords for ntsc and 1135 16-bit vbi data w ords for p al/secam for each line of analog video input at a clkx1 rate assuming a nominal or ideal video input signal (i.e., analog video signal has a stable horizontal time base). this is also equi v alent to 1820 8-bit vbi data samples for ntsc and 2270 8-bit vbi data samples for p al/secam for each line of analog video input. these v alues can de viate from the nominal depending on the actual line length of the analog video signal. vbi frame output mode is enabled via the vbifrm bit in the oform re gister . the output byte ordering may be controlled by the vbifmt bit as described for vbi line output mode. if both vbi line output and vbi frame output modes are en- abled at the same time, the vbi frame output mode tak es precedence. the vbi data range in vbi frame output mode can be controlled using the range bit in the oform re gister , and a video signal must be present on the bt829a analog input for this mode to operate as de ned by the status of the vpres bit in the st a tus re gister (0x00).
39 f unctional d escription closed captioning and extended data ser vices decoding l829a_b bt829a/827a v ideostr eam ii decoders closed captioning and extended data ser vices decoding in a system capable of capturing closed captioning (cc) and extended data ser - vices (eds) adhering to the eia-608 standard, tw o bytes of information are pre- sented to the video decoder on line 21 (odd eld) for cc and an additional tw o bytes are presented on line 284 (e v en eld) for eds. the data presented to the video decoder is an analog signal on the composite video input. the signal contains information identifying it as the cc/eds data and is follo wed by a control code and tw o bytes of digital information transmitted by the analog signal. f or the purposes of cc/eds, only the luma component of the video signal is rele v ant. therefore, the composite signal goes through the decima- tion and y/c separation blocks of the bt829a before an y cc/eds decoding tak es place. see figure 23 for a representation of this procedure. the bt829a can be programmed to decode cc/eds data via the corresponding bits in the extended data services/closed caption status re gister (cc_st a tus;0x1c). the cc and eds are independent and the video decoder may capture one or both in a gi v en frame. the cc/eds signal is displayed in figure 24 . in cc/eds decode mode, once bt829a has detected that line 21 of the eld is being displayed, the decoder looks for the clock run-in signal. if the clock run-in signal is present and the correct start code (001) is recognized by bt829a, then the cc/eds data capture commences. each of the tw o bytes of data transmit- ted to the video decoder per eld contains a 7-bit ascii code and a parity bit. the con v ention for cc/eds data is odd parity . figure 23. cc/eds data pr ocessing p ath decimation filter y/c separ ation filter inter polation filter adc composite analog ycrcb 4:2:2 cc/eds decoder cc/eds fifo cc_data register cc_status register i 2 c i 2 c luma
bt829a/827a v ideostr eam ii decoders 40 f unctional d escription closed captioning and extended data ser vices decoding l829a_b the bt829a pro vides a 16 x 10 location fifo for storing cc/eds data. once the video decoder detects the start signal in the cc/eds signal, it captures the lo w byte of cc/eds data rst and checks to see if the fifo is full. if the fifo is not full, then the data is stored in the fifo, and is a v ailable to the user through the cc_d a t a re gister (0x1d). the high byte of cc/eds data is captured ne xt and placed in the fifo. upon being placed in the 10-bit fifo, tw o additional bits are attached to the cc/eds data byte by bt829a s cc/eds decoder . these tw o bits indicate whether the gi v en byte stored in the fifo corresponds to cc or eds data and whether it is the high or lo w byte of cc/eds. these tw o bits are a v ailable to the user through the cc_st a tus re gister bits cc_eds and lo_hi, respecti v ely . the parity bit is stored in the fifo as sho wn in figure 25 . additionally , the bt829a stores the results of the parity check in the p arity_err bit in the cc_st a tus re gister . figure 24. cc/eds incoming signal s1 s2 s3 b0 b1 b2 b3 b4 b5 b6 p1 b0 b1 b2 b3 b4 b5 b6 p2 star t bits char acter one char acter t w o cloc k run-in color hsync burst 50 25 0 ?0 ire figure 25. closed captioning/extended data ser vices fifo location 0 location 1 location 15 9 8 7 6 0 msb lsb ... ... 7-bit ascii code a v ailab le through cc_d a t a regist e p ar ity bit a v ailab le through cc_d a t a register lo_hi a v ailab le through cc_st a tus register cc_eds a v ailab le through cc_st a tus register
41 f unctional d escription closed captioning and extended data ser vices decoding l829a_b bt829a/827a v ideostr eam ii decoders the 16-location fifo can hold eight lines w orth of cc/eds data, at tw o bytes per line. initially when the fifo is empty , bit d a in the cc_st a tus re gister (0x1c) is set lo w and indicates that no data is a v ailable in the fifo. subsequently , when data has been stored in the fifo, the d a bit is set to logical high. once the fifo is half full, the cc_v alid interrupts pin signals to the system that the fifo contents should be read in the near future. the cc_v alid pin is enabled via a bit in the cc_st a tus re gister (0x1c). the system controller can then poll the cc_v alid bit in the st a tus re gister (0x00) to ensure that it w as the bt829a that initiated the cc_v alid interrupt. this bit can also be used in applications where the cc_v alid pin is disabled by the user . when the rst byte of cc/eds data is decoded and stored in the fifo, the data is immediately placed in the cc_d a t a and cc_st a tus re gisters and is a v ail- able to be read. once the data is read from the cc_d a t a re gister , the information in the ne xt location of the fifo is placed in the cc_d a t a and cc_st a tus re g- isters. if the controller in the system ignores the bt829a cc_v alid interrupts pin for a suf ciently long period of time, then the cc/eds fifo will become full and the bt829a will not be able to write additional data to the fifo. an y incoming bytes of data will be lost and an o v er o w condition will occur; bit or in the cc_st a tus re gister will be set to a logical one. the system may clear the o v er - o w condition by reading the cc/eds data and creating space in the fifo for ne w information. as a result, the o v er o w bit is reset to a logical zero. there will routinely be asynchronous reads and writes to the cc/eds fifo. the writes will be from the cc/eds circuitry and the reads will occur as the sys- tem controller reads the cc/eds data from bt829a. these reads and writes will sometimes occur simultaneously , and the bt829a is designed to gi v e priority to the read operations. in the case where the cc_d a t a re gister data is speci cally being read to clear an o v er o w condition, the simultaneous occurrence of a read and a write will not cause the o v er o w bit to be reset, e v en though the read has priority . an additional read must be made to the cc_d a t a re gister in order to clear the o v er o w condition. as al w ays, the write data will be lost while the fifo is in o v er - o w condition. the fifo is reset when both cc and eds bits are disabled in the cc_st a tus re gister; an y data in the fifo is lost. a utomatic chr ominance gain contr ol the automatic chrominance gain control compensates for reduced chrominance and color -b urst amplitude. this can be caused by high-frequenc y loss in cabling. here, the color -b urst amplitude is calculated and compared to nominal. the col- or -dif ference signals are then increased or decreased in amplitude according to the color -b urst amplitude dif ference from nominal. the maximum amount of chromi- nance g ain is 0.5? times the original amplitude. this compensation coef cient is then multiplied by the v alue in the saturation adjust re gister for a total chromi- nance g ain range of 0? times the original signal. automatic chrominance g ain control may be disabled by setting the ca gc bit in the scloop re gister to a log- ical zero.
bt829a/827a v ideostr eam ii decoders 42 f unctional d escription closed captioning and extended data ser vices decoding l829a_b lo w color detection and remo v al if a color b urst of 25 percent (ntsc) or 35 percent (p al/secam) or less of the nominal amplitude is detected for 127 consecuti v e scan lines, the color -dif ference signals u and v are set to zero. when the lo w color detection is acti v e, the reduced chrominance signal is still separated from the composite signal to generate the lu- minance portion of the signal. the resulting cr and cb v alues are 128. output of the chrominance signal is re-enabled when a color b urst of 43 percent (ntsc) or 60 percent (p al/secam) or greater of nominal amplitude is detected for 127 con- secuti v e scan lines. lo w color detection and remo v al may be disabled by setting the ckill bit in the scloop re gister (0x10) to a logical zero. coring the bt829a video decoder can perform a coring function, in which it forces all v alues belo w a programmed le v el to be zero. this is useful because the human e ye is more sensiti v e to v ariations in black images. by taking near -black images and turning them into black, the image appears clearer to the e ye. f our coring v alues can be selected by the output f ormat re gister (oform; 0x12): 0, 8, 16, or 32 abo v e black. if the total luminance le v el is belo w the selected limit, the luminance signal is truncated to the black v alue. if the luma range is lim- ited (i.e., black is 16), then the coring circuitry automatically tak es this into ac- count and references the appropriate v alue for black. this is illustrated in figure 26 . figure 26. coring map 32 16 8 0 32 16 8 0 calculated luma v alue output luma v alue
43 l829a_b e lectrical i nterfaces input interface analog signal selection the bt829a/827a contains an on-chip 4:1 mux. f or the bt829a and BT827A, this multiple x er can be used to switch between four composite sources or three composite sources and one s-v ideo source. in the rst con guration, connect the inputs of the multiple x er (mux[0], mux[1], mux[2] and mux[3]) to the four composite sources. in the second con guration, connect three inputs to the com- posite sources and the other input to the luma component of the s-v ideo connector . in both con gurations the output of the multiple x er (muxout) should be con- nected to the input to the luma a/d (yin) and the input to the sync detection cir - cuitry (syncdet) through a optional 0.1 m f capacitor (to maintain compatibility with the bt829/827). when implementing s-v ideo, the input to the chroma a/d (cin) should be connected to the chroma signal of the s-v ideo connector . use of the multiple x er is not a requirement for operation. if digitization of only one video source is required, the source may be connected directly to yin. multiple x er considerations the multiple x er is not a break-before-mak e design. therefore, during the multi- ple x er switching time it is possible for the input video signals to be momentarily connected together through the equi v alent of 200 w . the multiple x ers cannot be switched on a real-time pix el-by-pix el basis. a utodetection of ntsc or p al/secam video if the bt829a is con gured to decode both ntsc and p al/secam, the bt829a can be programmed to automatically detect which format is being input to the chip. autodetection will select the proper clock source for the format detected. if ntsc/p al? is detected, xt al0 is selected. if p al/secam is detected, xt al1 is selected. f or p al-n combination the user must manually select the xt al0 crystal. full control of the decoding con guration can be programmed by writing to the input f ormat re gister (0x01).
bt829a/827a v ideostr eam ii decoders 44 e lectrical i nterfaces input interface l829a_b the bt829a determines the video source input to the chip by counting the num- ber of lines in a frame. bit numl indicates the result in the st a tus re gister . based on this bit, the format of the video is determined, and xt0 or xt1 is select- ed for the clock source. automatic format detection will select the clock source, b ut it will not program the required re gisters. the scaling and cropping re gisters (vscale, hscale, vdela y , hdela y , v a ctive, and ha ctive) as well as the b urst delay and a gc delay re gisters (bdela y and adela y) must be pro- grammed accordingly . flash a/d con ver ter s the bt829a and BT827A use tw o on-chip ash a/d con v erters to digitize the video signals. yref+, cref+ and yref? cref?are the respecti v e top and bottom of the internal resistor ladder . the input video is al w ays ac-coupled to the decoder . cref?and yref?are connected to analog ground. the v oltage le v els for yref+ and cref+ are con- trolled by the g ain control circuitry . if the input video momentarily e xceeds the corresponding ref+ v oltage it is indicated by lof and cof in the st a tus re g- ister . a/d clamping an internally generated clamp control signal is used to clamp the inputs of the a/d con v erter for dc restoration of the video signals. clamping for both the yin and cin analog inputs occurs within the horizontal sync tip. the yin input is al w ays restored to ground while the cin input is al w ays restored to clevel. clevel can be set with an optional e xternal resistor netw ork so that it is biased to the mid- point between cref?and cref+. this insures backw ard compatibility with bt819a/7a/5a b ut is not required for the bt829a/827a. external clamping is not required because internal clamping is automatically performed. p o wer -up operation upon po wer -up, the status of the bt829a s re gisters is indeterminate. the rst sig- nal must be asserted to set the re gister bits to their def ault v alues. the bt829a de- vice def aults to ntsc-m format upon reset. if pin 85 (oepole) is a logical high and the rst signal is asserted then the video pix el b us, sync signals, and output clocks will be three-stated. a utomatic gain contr ols the refout , cref+ and yref+ pins should be connected together as sho wn in figure 27 . in this con guration, the bt829a controls the v oltage for the top of the reference ladder for each a/d. the automatic g ain control adjusts the yref+ and cref+ v oltage le v els until the back porch of the y video input generates a digital code 0x38 from the a/d. if the video being digitized has a non-standard sync height to video height ratio, the digital code used for a gc may be changed by pro- gramming the adc interf ace re gister (0x1a). figure 28 illustrates bt829a e xter - nal circuitry with reduced passi v e components.
45 e lectrical i nterfaces input interface l829a_b bt829a/827a v ideostr eam ii decoders figure 27. bt829a t ypical external cir cuitr y f or bac kwar d compatibility with bt829/827 notes: (1). not required for bt829a/827a. shown for backward compatibility with the bt829/7. mux2 mux3 cin 0.1 m f 1 m w muxout yin syncdet cref yref clevel refout yref+ cref+ v aa 2 k w 0.1 m f 30 k w 30 k w 0.1 m f xt0i xt0o 2.7 m h 22 pf 33 pf 0.1 m f 28.63636 xt1i xt1o 2.2 m h 22 pf 33 pf 0.1 m f 35.46895 0.1 m f jt a g i 2 c video timing anti-aliasing filter 75 w t er mination a c coupling capacitor 1 m w 1 m w mhz mhz analog ground digital ground 0.1 m f v aa vpos a gccap vneg 75 w 1.0 m f mux0 75 w 330 pf 330 pf 1.0 m f 3.3 m h mux(0?) 75 w 1.0 m f 75 w 1.0 m f 75 w 0.1 m f optional ccv alid vdd 100 k w (1) (1) (1) (1) 75 w 1.0 m f mux1
bt829a/827a v ideostr eam ii decoders 46 e lectrical i nterfaces input interface l829a_b figure 28. bt829a t ypical external cir cuitr y (reduced p assive components) mux2 mux3 cin muxout yin syncdet cref yref clevel refout yref+ cref+ 0.1 m f xt0i xt0o 2.7 m h 22 pf 33 pf 0.1 m f 28.63636 xt1i xt1o 2.2 m h 22 pf 33 pf 0.1 m f 35.46895 0.1 m f jt a g i 2 c video timing anti-aliasing filter 75 w t er mination a c coupling capacitor 1 m w 1 m w mhz mhz analog ground digital ground 0.1 m f v aa vpos a gccap vneg 75 w 1.0 m f mux0 75 w 330 pf 330 pf 1.0 m f 3.3 m h mux(0?) 75 w 1.0 m f 75 w 1.0 m f 75 w 0.1 m f optional ccv alid vdd 100 k w 75 w 1.0 m f mux1 v aa 0.1 m f
47 e lectrical i nterfaces input interface l829a_b bt829a/827a v ideostr eam ii decoders cr ystal inputs and cloc k generation the bt829a has tw o pairs of pins: xt0i/xt0o and xt1i/xt1o. the y are used to input a clock source. if both ntsc and p al video are being digitized, both clock inputs must be implemented. the xt0 port is used to decode ntsc video and must be con gured with a 28.63636 mhz source. the xt1 port is used to decode p al video and must be con gured with a 35.46895 mhz source. if the bt829a is con gured to decode either ntsc or p al b ut not both, then only one clock source must be pro vided to the chip and it must be connected to the xt0i/xt0o port. if a crystal input is not used, the crystal ampli ers are internally shut do wn to sa v e po wer . crystals are speci ed as follo ws: 28.636363 mhz or 35.468950 mhz third o v ertone p arallel resonant 30 pf load capacitance 50 ppm series resistance 40 w or less the follo wing crystals are recommended for use with the bt829a: 1 standard crystal (818) 443-2121 2b ak28m636363gle30a 2b ak35m468950gle30a 2 mmd (714) 444-1402 a30aa3-28.63636 mhz a30aa3-35.46895 mhz 3 ged (619) 591-4170 pkhc49-28.63636-.030-005-40r, 3rd o v ertone crystal pkhc49-35.46895-.030-005-40r, 3rd o v ertone crystal 4 m-t ron (800) 762-8800 mp-1 28.63636, 3rd o v ertone crystal mp-1 35.46895, 3rd o v ertone crystal 5 monitor (619) 433-4510 mm49x3c3a-28.63636, 3rd o v ertone crystal mm49x3c3a-35.46895, 3rd o v ertone crystal 6 cts (815) 786-8411 r3b55a30-28.63636, 3rd o v ertone crystal r3b55a30-35.46895, 3rd o v ertone crystal 7 f ox (813) 693-0099 hc49u-28.63636, 3rd o v ertone crystal hc49u-35.46895, 3rd o v ertone crystal
bt829a/827a v ideostr eam ii decoders 48 e lectrical i nterfaces input interface l829a_b the tw o clock sources may be con gured with either single-ended oscillators, fundamental cut crystals or third o v ertone mode crystals, with parallel resonant. if single-ended oscillators are used the y must be connected to xt0i and xt1i. the clock source options and circuit requirements are sho wn in figure 29 . the clock source tolerance should be 50 parts-per -million (ppm) or less, b ut 100 ppm is acceptable. de vices that output cmos v oltage le v els are required. the load capacitance in the crystal con gurations may v ary depending on the magnitude of board parasitic capacitance. the bt829a is dynamic, and, to ensure proper opera- tion, the clocks must al w ays be running with a minimum frequenc y of 28.64 mhz. the clkx1 and clkx2 outputs from the bt829a are generated from xt0 and xt1 clock sources. clkx2 operates at the crystal frequenc y (8xfsc) while clkx1 operates at half the crystal frequenc y (4xfsc).
49 e lectrical i nterfaces input interface l829a_b bt829a/827a v ideostr eam ii decoders figure 29. cloc k options p al/secam thir d over tone mode cr ystal oscillator 2.2 m h 33 pf 0.1 m f 22 pf xt1i xt1o 35.46895 mhz ntsc thir d over tone mode cr ystal oscillator 2.7 m h 33 pf 0.1 m f 22 pf xt0i xt0o 28.63636 mhz xt1i xt1o xt0i xt0o 47 pf 47 pf 28.63636 mhz 47 pf 47 pf 35.46895 mhz p al/secam fundamental cr ystal oscillator ntsc fundamental cr ystal oscillator 1 m w 1 m w 1 m w 1 m w xt1i xt1o xt0i xt0o p al/secam single-ended oscillator ntsc single-ended oscillator osc osc 28.63636 mhz 35.46895 mhz
bt829a/827a v ideostr eam ii decoders 50 e lectrical i nterfaces input interface l829a_b 2x over sampling and input filtering t o a v oid aliasing artif acts, digitized video needs to be band-limited. because the bt829a samples at clkx2 (8xfsc? v er twice the normal rate), no ltering is re- quired at the input to the a/ds. the analog video needs to be band-limited to 14.32 mhz in ntsc and 17.73 mhz in p al/secam mode. normal video signals do not require additional e xternal ltering. ho we v er , if noise or other signal content is e xpected abo v e these frequencies, the optional anti-aliasing lter sho wn in figure 27 may be included in the input signal path. after digitization, the samples are digitally lo w-pass ltered and then decimated to clkx1. the response of the digital lo w-pass lter is sho wn in figure 30 . the digital lo w-pass lter pro vides the digital bandwidth reduction to limit the video to 6 mhz. figure 30. luma and chr oma 2x over sampling filter ntsc p al/secam ntsc p al/secam
51 e lectrical i nterfaces output interface l829a_b bt829a/827a v ideostr eam ii decoders output interface output interfaces the bt829a supports a synchronous pix el interf ace (spi). spi can support 8-bit or 16-bit ycrcb 4:2:2 data streams. bt829a outputs all pix el and control data synchronous with clkx1 (16-bit mode), or clkx2 (8-bit mode). ev ents such as hreset and vreset may also be encoded as control codes in the data stream to enable a reduced pin interf ace (bytestream ? ). mode selections are controlled by the state of the oform re gister (0x12). figure 31 sho ws a diagram summarizing the dif ferent operating modes. each mode will be co v ered in detail indi vidually . on po wer -up, the bt829a automati- cally initializes to spi mode 1, 16 bits wide. ycrcb pix el stream format, spi mode 8- and 16-bit formats when the output is con gured for an 8-bit pix el interf ace, the data is output on pins vd[15:8] with eight bits of chrominance data preceding eight bits of luminance data for each pix el. ne w pix el data is output on the pix el port after each rising edge of clkx2. when the output is con gured for the 16-bit pix el interf ace, the lumi- nance data is output on vd[15:8], and the chrominance data is output on vd[7:0]. in 16-bit mode, the data is output with respect to clkx1. see t able 7 for a sum- mary of output interf ace con gurations. the ycrcb 4:2:2 pix el stream follo ws the ccir recommendation as illustrated in figure 32 . figure 31. output mode summar y spi 8-bit 16-bit 8-bit 16-bit p ar allel control (spi mode 1) coded control (spi mode 2) (bytestream )
bt829a/827a v ideostr eam ii decoders 52 e lectrical i nterfaces output interface l829a_b t ab le 7. pix el/pin map 16-bit pix el interface pin name vd 15 vd 14 vd 13 vd 12 vd 11 vd 10 vd 9 vd 8 vd 7 vd 6 vd 5 vd 4 vd 3 vd 2 vd 1 vd 0 data bit y7 y6 y5 y4 y3 y2 y1 y0 cr cb 7 cr cb 6 cr cb 5 cr cb 4 cr cb 3 cr cb 2 cr cb 1 cr cb 0 8-bit pix el interface pin name vd 15 vd 14 vd 13 vd 12 vd 11 vd 10 vd 9 vd 8 vd 7 vd 6 vd 5 vd 4 vd 3 vd 2 vd 1 vd 0 y data bit y7 y6 y5 y4 y3 y2 y1 y0 c data bit cr cb 7 cr cb 6 cr cb 5 cr cb 4 cr cb 3 cr cb 2 cr cb 1 cr cb 0 figure 32. ycrcb 4:2:2 pix el stream format (spi mode , 8 and 16 bits) 8-bit pix el interf ace clkx1 16-bit pix el interf ace cb0 y0 cr0 y1 cb2 y2 cr2 y3 cb0 cr0 y0 y1 cb2 cr2 y2 y3 vd[15:8] vd[15:8] vd[7:0] clkx2
53 e lectrical i nterfaces output interface l829a_b bt829a/827a v ideostr eam ii decoders sync hr onous pix el interface (spi, mode 1) upon reset, the bt829a initializes to the spi output mode 1. in this mode, bt829a outputs all horizontal and v ertical blanking interv al pix els in addition to the acti v e pix els synchronous with clkx1 (16-bit mode), or clkx2 (8-bit mode). figure 33 illustrates bt829a spi-1. the basic timing relationships remain the same for the 16-bit or 8-bit modes. the 16-bit modes use clkx1 as the reference, and the 8-bit modes use clkx2. figure 34 sho ws the video timing for spi mode 1. figure 33. bt829a/827a sync hr onous pix el interface , mode 1 (spi-1) hreset vreset a ctive d v alid cbfla g field vd[15:0] oe 16 clkx1 (4*fsc) bt829a clkx2 (8*fsc) qclk figure 34. basic timing relationships f or spi mode 1 vd[15:0] d v alid a ctive clkx1 or clkx2 qclk cbfla g
bt829a/827a v ideostr eam ii decoders 54 e lectrical i nterfaces output interface l829a_b sync hr onous pix el interface (spi, mode 2, bytestream) in spi mode 2, the bt829a encodes all video timing control signals onto the pix el data b us. bytestream is the 8-bit v ersion of this con guration. because all tim- ing data is included on the data b us, a complete interf ace to a video controller can be implemented in only nine pins: one for clkx2 and eight for data. when using coded control, the range bit and the code bit must be pro- grammed high. when the range bit is high, the chrominance pix els (both cr and cb) are saturated to the range 2 to 253, and the luminance range is limited to the range 16 to 253. in spi mode 2, the chroma v alues of 255 and 254, and the lumi- nance v alues of 0 to 15 are inserted as control codes to indicate video e v ents ( t able 8 ). a chroma v alue of 255 is used to indicate that the associated luma pix el is a control code; a pix el v alue of 255 also indicates that the cbflag is high (i.e., the current pix el is a cb pix el). similarly , a pix el v alue of 254 indicates that the luma v alue is a control code, and the cbflag is lo w (cr pix el). the rst pix el of a line is guaranteed to be a cb ag, ho we v er , due to code pre- cedence relationships, the hreset code may be delayed by one pix el, so hreset can occur on a cr or a cb pix el. also, at the be ginning of a ne w eld the relationship between vreset and hreset may be lost, typically with video from a vcr. as a result, vreset can occur during either a cb or a cr pix el. figure 35 demonstrates coded control for spi mode 2 (bytestream). pix el data output ranges are sho wn in t able 9 . independent of range, decimal 128 indicates zero color information for cr and cb . black is decimal 16 when range = 0, and code 0 when range = 1. figures 36 and 37 illustrate videotiming for both spi modes 1 and 2. t ab le 8. description of the contr ol codes in the pix el stream luma v alue chr oma v alue video event description 0x00 0xff 0xfe this is an in v alid pix el; last v alid pix el w as a cb pix el. this is an in v alid pix el; last v alid pix el w as a cr pix el. 0x01 0xff 0xfe cb pix el; last pix el w as the last activ e pix el of the line . cr pix el; last pix el w as the last activ e pix el of the line . 0x02 0xff 0xfe cb pix el; ne xt pix el is the rst activ e pix el of the line . cr pix el; ne xt pix el is the rst activ e pix el of the line . 0x03 0xff 0xfe cb pix el; hreset of a v er tical activ e line . cr pix el; hreset of a v er tical activ e line . 0x04 0xff 0xfe cb pix el; hreset of a v er tical b lank line . cr pix el; hreset of a v er tical b lank line . 0x05 0xff 0xfe cb pix el; vreset f ollo w ed b y an e v en eld. cr pix el; vreset f ollo w ed b y an e v en eld. 0x06 0xff 0xfe cb pix el; vreset f ollo w ed b y an odd eld. cr pix el; vreset f ollo w ed b y an odd eld.
55 e lectrical i nterfaces output interface l829a_b bt829a/827a v ideostr eam ii decoders figure 35. data output in spi mode 2 (bytestream) clkx2 vd(15:8) 0xff 0x04 0xff 0x03 ?? hreset , beginning of hor iz ontal line dur ing activ e video cb pix el cb pix el hreset : beginning of hor iz ontal line dur ing v er tical b lanking ?? ?? ?? ?? ?? ?? ?? ?? ?? 0xff 0x02 cb y cr y first activ e pix el of the line in v alid pix el dur ing activ e video last v alid pix el w as a cb pix el cb y 0xff 0x00 cr y cb y 0xfe 0x01 xx xx last pix el of the line (cb pix el) last pix el code (cr pix el) cr pix el vreset : an odd eld f ollo ws xx xx 0xfe 0x06 xx xx activ e pix el of the line ne xt pix el is rst
bt829a/827a v ideostr eam ii decoders 56 e lectrical i nterfaces output interface l829a_b figure 36. video timing in spi modes 1 and 2 notes: (1). hreset precedes vreset by two clock cycles at the beginning of fields 1, 3, 5 and 7 to facilitate external field generation. 2. a ctive pin ma y be prog r ammed to be composite a ctive or hor iz ontal a ctive. 3. a ctive, hreset , vreset and field are sho wn here with their def ault polar ity . the polar ity is prog r am- mab le via the vpole register . 4. field tr ansitions with the end of hor iz ontal activ e video de ned b y hdela y and ha ctive. 2? scan lines hreset vreset a ctive field vdela y/2 scan lines beginning of elds 1, 3, 5, 7 (1) 2? scan lines hreset vreset a ctive field vdela y/2 scan lines beginning of elds 2, 4, 6, 8
57 e lectrical i nterfaces output interface l829a_b bt829a/827a v ideostr eam ii decoders ccir601 compliance when the range bit is set to zero, the output le v els are fully compliant with the ccir601 recommendation. ccir601 speci es that nominal video will ha v e y v al- ues ranging from 16 to 235, and cr and cb v alues ranging from 16 to 240. ho w- e v er , e xcursions outside this range are allo wed to handle non-standard video. the only mandatory requirement is that 0 and 255 be reserv ed for timing information. figure 37. horizontal timing signals in the spi modes hdela y cloc k cycles at fdesired ha ctive cloc k cycles at fdesired 64 cloc k cycles at fclkx1 hreset a ctive t ab le 9. data output rang es range = 0 range = 1 y 16 ? 235 0 ? 255 cr 2 ? 253 2 ? 253 cb 2 ? 253 2 ? 253
bt829a/827a v ideostr eam ii decoders 58 e lectrical i nterfaces i 2 c interface l829a_b i 2 c interface the inter -inte grated circuit b us is a tw o-wire serial interf ace. serial clock (scl) and data lines (sd a), are used to transfer data between the b us master and the sla v e de vice. the bt829a can transfer data at a maximum rate of 100 kbits/s. the bt829a operates as a sla v e de vice. star ting and stopping the relationship between scl and sd a is decoded to pro vide both a start and stop condition on the b us. t o initiate a transfer on the i 2 c b us, the master must transmit a start pulse to the sla v e de vice. this is accomplished by taking the sd a line lo w while the scl line is held high. the master should only generate a start pulse at the be ginning of the c ycle, or after the transfer of a data byte to or from the sla v e. t o terminate a transfer , the master must tak e the sd a line high while the scl line is held high. the master may issue a stop pulse at an y time during an i 2 c c ycle. since the i 2 c b us will interpret an y transition on the sd a line during the high phase of the scl line as a start or stop pulse, care must be tak en to ensure that data is stable during the high phase of the clock. this is illustrated in figure 38 . ad dressing the bt829a an i 2 c sla v e address consists of tw o parts: a 7-bit base address and a single bit r/ w command. the r/ w bit is appended to the base address to form the transmit- ted i 2 c address, as sho wn in figure 39 and t able 10 . figure 38. the relationship between scl and sd a star t stop sd a scl figure 39. i 2 c sla ve ad dress con guration a6 a5 a4 a3 a2 a1 a0 r/ w base address r/w bit
59 e lectrical i nterfaces i 2 c interface l829a_b bt829a/827a v ideostr eam ii decoders reading and writing after transmitting a start pulse to initiate a c ycle, the master must address the bt829a. t o do this, the master must transmit one of the four v alid bt829a address- es, most signi cant bit (msb) rst. after transmitting the address, the master must release the sd a line during the lo w phase of the scl and w ait for an ac- kno wledge. if the transmitted address matches the selected bt829a address, the bt829a will respond by dri ving the sd a line lo w , generating an ackno wledge to the master . the master will sample the sd a line at the rising edge of the scl line, and proceed with the c ycle. if no de vice responds, including the bt829a, the mas- ter transmits a stop pulse and ends the c ycle. if the sla v e address r/ w bit w as lo w (indicating a write) the master will transmit an 8-bit byte to the bt829a, msb rst. the bt829a will ackno wledge the transfer and load the data into its internal address re gister . the master can no w issue a stop command, a start command, or transfer another 8-bit byte, msb rst, to be loaded into the re gister pointed to by the internal address re gister . the bt829a will then ackno wledge the transfer and increment the address re gister in preparation for the ne xt transfer . as before, the master may no w issue a stop command, a start com- mand, or transfer another 8 bits to be loaded into the ne xt location. if the sla v e address r/ w bit w as high (indicating a read) the bt829a will trans- fer the contents of the re gister pointed to by its internal address re gister , msb rst. the master should ackno wledge the receipt of the data and pull the sd a line lo w . as with the write c ycle, the address re gister will be auto-incremented in prepara- tion for the ne xt read. t o stop a read transfer , the host must not ackno wledge the last read c ycle. the bt829a will then release the data b us in preparation for a stop command. if an ac- kno wledge is recei v ed, the bt829a will proceed to transfer the ne xt re gister . when the master generates a read from the bt829a, the bt829a will start its transfer from whate v er location is currently loaded in the address re gister . since the address re gister might not contain the address of the desired re gister , the master should e x ecute a write c ycle, setting the address re gister to the desired location. after recei ving an ackno wledge for the transfer of the data into the address re gister , the master should initiate a read of the bt829a by starting a ne w i 2 c c ycle with an appropriate read address. the bt829a no w transfers the contents of the desired re gister . t ab le 10. bt829a ad dress matrix i2ccs pin bt829a base r/ w bit action 0 1000100 0 wr ite 1000100 1 read 1 1000101 0 wr ite 1000101 1 read
bt829a/827a v ideostr eam ii decoders 60 e lectrical i nterfaces i 2 c interface l829a_b f or e xample, to read re gister 0x0a, brightness control, the master should start a write c ycle with an i 2 c address of 0x88 or 0x8a. after recei ving an ackno wledge from the bt829a, the master should transmit the desired address, 0x0a. after re- cei ving an ackno wledge, the master should then start a read c ycle with an i 2 c sla v e address of 0x89 or 0x8b. the bt829a will then ackno wledge and transfer the con- tents of re gister 0x0a. there is no need to issue a stop command after the write c y- cle. the bt829a will detect the repeated start command, and start a ne w i 2 c c ycle. this process is illustrated in t able 11 and figure 40 . f or detailed information on the i 2 c b us, refer to ?he i 2 c-bus refer ence guide,? reprinted by rockwell. t ab le 11. example i 2 c data t ransactions master data flo w bt829a comment write to bt829a i 2 c star t > master sends bt829a chip address , i.e ., 0x88 or 0x8a. a ck bt829a gener ates a ck on successful receipt of chip address . sub-address > master sends sub-address to bt829a. a ck bt829a gener ates a ck on successful receipt of sub-address . data(0) > master sends rst data b yte to bt829a. a ck(0) bt829a gener ates a ck on successful receipt of 1st data b yte . . . . > > > . . . data(n) > master sends nth data b yte to bt829a. a ck(n) bt829a gener ates a ck on successful receipt of nth data b yte . i 2 c stop master gener ates st op to end tr ansf er . read fr om bt829a i 2 c star t > master sends bt829a chip address , i.e ., 0x89 or 0x8b . a ck bt829a gener ates a ck on successful receipt of chip address . < data(0) bt829a sends rst data b yte to master . a ck(0) master gener ates a ck on successful receipt of 1st data b yte . . . . < < < . . . < data(n-1) bt829a sends (n-1)th data b yte to master . a ck(n-1) master gener ates a ck on successful receipt of (n-1)th data b yte . < data(n) bt829a sends nth data b yte to master . no a ck master does not ac kno wledge nth data b yte . i 2 c stop master gener ates st op to end tr ansf er .
61 e lectrical i nterfaces i 2 c interface l829a_b bt829a/827a v ideostr eam ii decoders software reset the contents of the control re gisters may be reset to their def ault v alues by issuing a softw are reset. a softw are reset can be accomplished by writing an y v alue to subaddress 0x1f . a read of this location will return an unde ned v alue. where: i 2 c star t = i 2 c start condition and bt829a chip address (including the r/ w bit). sub-address = the 8-bit sub-address of the bt829a register, msb first. data(n) = the data to be transferred to/from the addressed register. i 2 c stop = i 2 c stop condition. figure 40. i 2 c pr otocol dia gram chip addr d a t a s a sr a a chip addr sub-addr s a a a a p chip addr sub-addr s a a chip addr a d a t a d a t a d a t a data read data wr ite wr ite f ollo w ed b y read 0x89 or 0x8b repeated 8 bits f rom master to bt829a f rom bt829a to master s = start sr = repeated start p = stop a = acknowledge na = non acknowledge 0x88 or 0x8a 0x88 or 0x8a na p d a t a d a t a a a a a d a t a data na p d a t a a register p ointed to b y subaddress star t
bt829a/827a v ideostr eam ii decoders 62 e lectrical i nterfaces jt a g interface l829a_b jt a g interface need f or functional v eri cation as the comple xity of imaging chips increases, the need to easily access indi vidual chips for functional v eri cation is becoming vital. the bt829a has incorporated special circuitry that allo ws it to be accessed in full compliance with standards set by the joint t est action group. conforming to ieee p1149.1 ?tandard t est ac- cess port and boundary scan architecture, ?the bt829a has dedicated pins that are used for testability purposes only . jt a g appr oac h to t estability jt a g s approach to testability utilizes boundary scan cells placed at each digital pin and digital interf ace (a digital interf ace is the boundary between an analog block and a digital block within the bt829a). all cells are interconnected into a boundary scan re gister that applies or captures test data to v erify functionality of the inte grated circuit. jt a g is particularly useful for board testers using functional testing methods. jt a g consists of v e dedicated pins comprising the t est access port (t ap). these pins are t est mode select (tms), t est clock (tck), t est data input (tdi), t est data out (tdo) and t est reset ( trst ). the trst pin will reset the jt a g controller when pulled lo w at an y time. v eri cation of the inte grated circuit and its connection to other modules on the printed circuit board can be achie v ed through these v e t ap pins. w ith boundary scan cells at each digital interf ace and pin, the bt829a has the capability to apply and capture the respecti v e logic le v els. because all of the digital pins are interconnected as a long shift re gister , the t ap logic has access and control of all the necessary pins to v erify functionality . the t ap con- troller can shift in an y number of test v ectors through the tdi input and apply them to the internal circuitry . the output result is scanned out on the tdo pin and e x- ternally check ed. while isolating the bt829a from other components on the board, the user has easy access to all bt829a digital pins and digital interf aces through the t ap and can perform complete functionality tests without using e xpensi v e bed-of-nails testers. optional de vice id register the bt829a has the optional de vice identi cation re gister de ned by the jt a g speci cation. this re gister contains information concerning the re vision, actual part number , and manuf acturers identi cation code speci c to rockwell. this re g- ister can be accessed through the t ap controller via an optional jt a g instruction. refer to t able 12 .
63 e lectrical i nterfaces jt a g interface l829a_b bt829a/827a v ideostr eam ii decoders v eri cation with the t ap contr oller a v ariety of v eri cation procedures can be performed through the t ap controller . using a set of four instructions, the bt829a can v erify board connecti vity at all digital interf aces and pins. the instructions can be accessed by using a state ma- chine standard to all jt a g controllers and are sample/preload, extest, id code, and bypass (see figure 41 ). refer to the ieee p1149.1 speci cation for details concerning the instruction re gister and jt a g state machine. rockwell has created a bsdl with the a t&t bsd editor . should jt a g testing be implemented, a disk with an ascii v ersion of the complete bsdl le can be obtained by contacting your local rockwell sales of ce. t ab le 12. de vice identi cation register v er sion p ar t number man ufacturer id x x x x 0 0 0 0 0 0 1 1 0 0 1 1 1 1 0 1 0 0 0 1 1 0 1 0 1 1 0 1 0 0829, 0x033d 0x0d6 4 bits 16 bits 11 bits note: the part number remains the same for both parts: bt829a and BT827A. figure 41. instruction register tdi tdo extest 0 0 sample/preload 0 0 id code 0 1 bypass 1 1
bt829a/827a v ideostr eam ii decoders 64 e lectrical i nterfaces jt a g interface l829a_b example bsdl listing attribute boundary_register of bt829a : entity is ? 0 (bc_1, *, control, 1),?& ? 1 (bc_1, *, internal, 1),?& ? 2 (bc_1, *, control, 1),?& ? 3 (bc_1, *, internal, x),?& ? 4 (bc_1, *, internal, x),?& ? 5 (bc_1, *, internal, x),?& ? 6 (bc_1, *, internal, x),?& ? 7 (bc_1, *, internal, x),?& ? 8 (bc_1, *, internal, x),?& ? 9 (bc_1, *, internal, x),?& ? 10 (bc_1, *, internal, x),?& ? 11 (bc_1, *, internal, x),?& ? 12 (bc_1, *, internal, x),?& ? 13 (bc_1, *, internal, 0),?& ? 14 (bc_1, *, internal, 0),?& ? 15 (bc_1, *, internal, 0),?& ? 16 (bc_1, *, internal, 0),?& ? 17 (bc_1, *, internal, 0),?& ? 18 (bc_1, *, internal, 0),?& ? 19 (bc_1, *, internal, 0),?& ? 20 (bc_1, *, internal, 0),?& ? 21 (bc_1, *, internal, 0),?& ? 22 (bc_1, *, internal, 0),?& ? 23 (bc_1, *, internal, 0),?& ? 24 (bc_1, *, internal, 0),?& ? 25 (bc_1, *, internal, 0),?& ? 26 (bc_1, *, internal, 0),?& ? 27 (bc_1, *, internal, 0),?& ? 28 (bc_1, *, control, 0),?& ? 29 (bc_1, field, output3, x, 28, 0, z),?& ? 30 (bc_1, nvreset, output3, x, 28, 0, z),?& ? 31 (bc_1, xtfmt, input, x),?& ? 32 (bc_1, nhreset, output3, x, 28, 0, z),?& ? 33 (bc_1, active, output3, x, 28, 0, z),?& ? 34 (bc_1, dvalid, output3, x, 28, 0, z),?& ? 35 (bc_1, vactive, output3, x, 28, 0, z),?& ? 36 (bc_1, tst, output2, 0, 36, 0, weak1),?& ? 37 (bc_1, *, internal, x),?& ? 38 (bc_1, cbflag, output3, x, 28, 0, z),?& ? 39 (bc_3, nvsen, input, x),?& ? 40 (bc_1, pwrdn, input, x),?& ? 41 (bc_1, qclk, output3, x, 28, 0, z),?& ? 42 (bc_1, clkx1, output3, x, 28, 0, z),?& ? 43 (bc_1, noe, input, 1),?& ? 44 (bc_1, clkx2, output3, x, 28, 0, z),?& ? 45 (bc_1, vdb(13), output3, x, 28, 0, z),?&
65 e lectrical i nterfaces jt a g interface l829a_b bt829a/827a v ideostr eam ii decoders ? 46 (bc_1, vdb(14), output3, x, 28, 0, z),?& ? 47 (bc_1, vdb(15), output3, x, 28, 0, z),?& ? 48 (bc_1, vdb(8), output3, x, 28, 0, z),?& ? 49 (bc_1, vdb(9), output3, x, 28, 0, z),?& ? 50 (bc_1, vdb(10), output3, x, 28, 0, z),?& ? 51 (bc_1, vdb(11), output3, x, 28, 0, z),?& ? 52 (bc_1, vdb(12), output3, x, 28, 0, z),?& ? 53 (bc_1, *, internal, x),?& ? 54 (bc_1, xt0i, input, x),?& ? 55 (bc_1, i2ccs, input, x),?& ? 56 (bc_1, nrst, input, x),?& ? 57 (bc_1, *, internal, x),?& ? 58 (bc_1, xt1i, input, x),?& ? 59 (bc_1, sda, output2, 0, 59, 1, pull1),?& ? 60 (bc_1, sda, input, x),?& ? 61 (bc_1, scl, input, x),?& ? 62 (bc_1, vda(3), output3, x, 0, 1, z),?& ? 63 (bc_1, vda(3), input, x),?& ? 64 (bc_1, vda(4), output3, x, 2, 1, z),?& ? 65 (bc_1, vda(4), input, x),?& ? 66 (bc_1, vda(5), output3, x, 2, 1, z),?& ? 67 (bc_1, vda(5), input, x),?& ? 68 (bc_1, vda(6), output3, x, 2, 1, z),?& ? 69 (bc_1, vda(6), input, x),?& ? 70 (bc_1, vda(7), output3, x, 2, 1, z),?& ? 71 (bc_1, vda(7), input, x),?& ? 72 (bc_1, vda(0), output3, x, 0, 1, z),?& ? 73 (bc_1, vda(0), input, x),?& ? 74 (bc_1, vda(1), output3, x, 0, 1, z),?& ? 75 (bc_1, vda(1), input, x),?& ? 76 (bc_1, vda(2), output3, x, 0, 1, z),?& ? 77 (bc_1, vda(2), input, x),?& ? 78 (bc_1, twren, input, x),?& ? 79 (bc_0, *, internal, 0),?& ? 80 (bc_0, *, internal, 0)? end bt829a;
bt829a/827a v ideostr eam ii decoders 66 e lectrical i nterfaces jt a g interface l829a_b
67 l829a_b pc b oard l ayout c onsiderations the layout should be optimized for lo west noise on the bt829a po wer and ground lines by shielding the digital inputs and outputs and pro viding good decoupling. the lead length between groups of po wer and ground pins should be minimized to reduce inducti v e ringing. gr ound planes the ground plane area should encompass all bt829a ground pins, v oltage refer - ence circuitry , po wer supply bypass circuitry for the bt829a, the analog input trac- es, an y input ampli ers, and all the digital signal traces leading to the bt829a. the bt829a has digital grounds (gnd) and analog grounds (a gnd and vneg). the layout for the ground plane should be such that the tw o planes are at the same electrical potential, b ut the y should be isolated from each other in the ar - eas surrounding the chip. also, the return path for the current should be through the digital plane. see figure 42 for an e xample of ground plane layout. figure 42. example gr ound plane la y out bt829a 1 50 analog ground digital ground ground retur n (i.e ., isa bus connection) circuit board edge
bt829a/827a v ideostr eam ii decoders 68 pc b oard l ayout c onsiderations p o wer planes l829a_b p o wer planes the po wer plane area should encompass all bt829a po wer pins, v oltage reference circuitry , po wer supply bypass circuitry for the bt829a, the analog input traces, an y input ampli ers, and all the digital signal traces leading to the bt829a. the bt829a has digital po wer (vdd) and analog po wer (v aa and vpos). the layout for the po wer plane should be such that the tw o planes are at the same elec- trical potential, b ut the y should be isolated from each other in the areas surround- ing the chip. also, the return path for the current should be through the digital plane. this is the same layout as sho wn for the ground plane ( figure 42 ). when us- ing a re gulator , circuitry must be included to ensure proper po wer sequencing. the circuitry sho wn in figure 43 illustrates this circuitry layout. suppl y decoupling the bypass capacitors should be installed with the shortest leads possible (consis- tent with reliable operation) to reduce the lead inductance. these capacitors should also be placed as close as possible to the de vice. each group of v aa and vdd pins should ha v e a 0.1 m f ceramic bypass capac- itor to ground, located as close as possible to the de vice. additionally , 10 m f capacitors should be connected between the analog po wer and ground planes, as well as between the digital po wer and ground planes. these capacitors are at the same electrical potential, b ut pro vide additional decoupling by being ph ysically close to the bt829a po wer and ground planes. see figure 44 for additional information about po wer supply decoupling. figure 43. optional regulator cir cuitr y in system p o w er v aa, vdd out ground gnd suggested p ar t numbers: regulator t e xas instr uments m a78 mo5m (+5 v) system p o w er (+5 v) (+12 v) diodes must handle of the bt829a and the p er ipher al circuitr y the current requirements
69 pc b oard l ayout c onsiderations suppl y decoupling l829a_b bt829a/827a v ideostr eam ii decoders figure 44. t ypical p o wer and gr ound connection dia gram and p ar ts list +5 v (vcc) ground + + c1 c3 c4 vdd v aa, vpos gnd bt829a a gnd , vneg + analog area + c2 location description v endor p ar t number c1, c2 (1) 0.1 m f cer amic capacitor er ie rpe112z5u104m50v c3, c4 (2) 10 m f tantalum capacitor mallor y csr13g106km notes: (1). a 0.1 m f capacitor should be connected between each group of power pins and ground as close to the device as possible (ceramic chip capacitors are preferred). (2). the 10 m f capacitors should be connected betw een the analog supply and the analog g round, as w ell as the digital supply and the digital g round. these should be connected as close to the bt829a as possib le . 3. v endor n umbers are listed only as a guide . substitution of de vices with similar char acter istics will not aff ect the perf or mance of the bt829a.
bt829a/827a v ideostr eam ii decoders 70 pc b oard l ayout c onsiderations digital signal inter connect l829a_b digital signal inter connect the digital signals of the bt829a should be isolated as much as possible from the analog signals and other analog circuitry . also, the digital signals should not o v er - lay the analog po wer plane. an y termination resistors for the digital signals should be connected to the re g- ular pcb po wer and ground planes. analog signal inter connect long lengths of closely spaced parallel video signals should be a v oided to mini- mize crosstalk. ideally , there should be a ground line between the video signal trac- es dri ving the yin and cin inputs. also, high-speed ttl signals should not be routed close to the analog signals to minimize noise coupling. latc h-up a v oidance latch-up is a f ailure mechanism inherent to an y cmos de vice. it is triggered by static or impulse v oltages on an y signal input pin e xceeding the v oltage on the po wer pins by more than 0.5 v , or f alling belo w the gnd pins by more than 0.5 v . latch-up can also occur if the v oltage on an y po wer pin e xceeds the v oltage on an y other po wer pin by more than 0.5 v . in some cases, de vices with mix ed signal interf aces, such as the bt829a, can appear more sensiti v e to latch-up. in reality , this is not the case. ho we v er , mix ed signal de vices tend to interact with peripheral de vices such as video monitors or cameras that are referenced to dif ferent ground potentials, or apply v oltages to the de vice prior to the time that its po wer system is stable. this interaction sometimes creates conditions amenable to the onset of latch-up. t o maintain a rob ust design with the bt829a, the follo wing precautions should be tak en: apply po wer to the de vice before or at the same time as the interf ace cir - cuitry . do not apply v oltages belo w gnd?.5 v , or higher than v aa+0.5 v to an y pin on the de vice. do not use ne g ati v e supply op-amps or an y other ne g ati v e v oltage interf ace circuitry . all logic inputs should be held lo w until po wer to the de vice has settled to the speci ed tolerance. connect all vdd, v aa and vpos pins together through a lo w imped- ance plane. connect all gnd, a gnd and vneg pins together through a lo w imped- ance plane. sample sc hematics figures 45 through 47c are e xample schematics which detail the interf ace of the bt829a to cirrus logic, s3, and t rident v ga controllers. f or interf acing to a ti v ga controllers, please contact a ti t echnologies. f or interf acing to all other v ga controllers, please contact your local rockwell semiconductor sales of ce.
71 pc b oard l ayout c onsiderations sample sc hematics l829a_b bt829a/827a v ideostr eam ii decoders figure 45. bt829/cirrus logic 544x v ga interface sc hematic 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 a a b b c c d d i2c addr ess 0x8 8 without shunt 0 x8a with shunt install resistor if both crystals present b a x yout 0 0 xy0 0 1 xy1 1 0 xy2 1 1 xy3 mute t uner mute line select tun er select l ine antenna inpu t i2c addr ess 0x 8a without shunt 0x80 with shun t ground s are sperated by air g aps in the plane. tuesday, october 01, 1996 decode3.sch g 544x tv tuner pci board pixel semiconductor 5068 w. plano pkwy suite 350 plano, tx. 75093 c 4 5 title size document number rev date: shee t of vset vout vt vt +9v avdd avdd iswc lout +12v conv rout audiosel rsc audiomute auxoutl auxoutl mal auxinl auxinl +5 tuner +5 tuner cta auxoutr auxoutr mar tvideo auxinr auxinr taudio audio_in_r audio_in_r audio_in_l audio_in_l audio_out_r audio_out_r audio_out_l audio_out_l caudiol compv compv caudior chromv chromv chromin chromin lumv lumv lumin lumin compos p7 p6 p5 p4 p3 p2 p1 p0 vact valid active href href vactena* vref vref qvact clkx2 btena* btena* audiosel audiomute p[0..7] p[0..7] 12vl vcc vcc +12v vdd vaa vcc vcc +12v agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd vcc vcc vcc vcc c2 2.2uf a + l9 33uh 43fs r12 56k 805 c29 560pf 805 u4 mc34063 8 so comp 5 pwr 6 ipk 7 gnd 4 tcap 3 iswe 2 iswc 1 idc 8 r1 22k 805 l13 33uh 43fs c25 10uf d 35v + u1 tuner2 fi1236 video in 1 +33v 11 +5v 12 scl 13 sda 14 video out 23 +5v if 24 audio 25 t1 2 t2 3 t3 4 t4 5 c62 2.2uf a 16v + l11 33uh 43fs d1 1n4003 do-41 r22 20 805 c31 33pf 805 c50 .1uf 805 c56 22pf 805 c61 .1uf 805 c69 22pf 805 c57 33pf 805 r4 30k 805 r6 30k 805 r5 2k 805 r17 1m 805 r3 1k 805 c66 .1uf 805 c18 .1uf 805 c55 .1uf 805 c16 .1uf 805 u5 bt829 100qfp yin 52 syncdet 59 mux0 55 mux1 57 mux2 45 muxout 53 cin 67 agccap 41 refout 43 yref+ 49 yref- 62 cref+ 64 cref- 73 clevel 74 yabias 51 ycbias 46 ydbias 50 cabias 70 ccbias 69 cdbias 63 vd15 2 vd14 3 vd13 4 vd12 5 vd11 6 vd10 7 vd9 8 vd8 9 vd7 22 vd6 23 vd5 24 vd4 25 vd3 26 vd2 27 vd1 28 vd0 29 clkx1 97 clkx2 99 dvalid 84 hreset 82 vreset 79 active 83 qclk 94 oe 98 field 78 cbflag 89 ccvalid 87 vactive 86 pwrdn 91 numxtal 80 xt0 i 12 xt0 o 13 xt1 i 16 xt1 o 17 rst 15 scl 19 sda 18 i2ccs 14 trst 35 tms 36 tdo 32 tdi 37 tck 34 c1 .01uf 805 c65 10uf b + c53 10uf b + r15 2.2k 805 r25 1m 805 r18 1m 805 r21 1.6k 805 l1 3.3mh 8rb l6 3.3uh 805 r16 75 805 r13 75 805 c13 330pf 805 c27 330pf 805 c30 .1uf 805 c54 .1uf 805 l10 2.7uh 805 l8 2.2uh 805 u10 fct253 so16 1c0 6 1c1 5 1c2 4 1c3 3 2c0 10 2c1 11 2c2 12 2c3 13 a 14 b 2 ea 1 eb 15 1y 7 2y 9 r51 6.8k r50 33 805 jp3 minidin 9 mdin9 1 2 3 4 5 6 10 11 12 7 8 9 u11 pcf8574 so16w d7 12 d6 11 d5 10 d4 9 d3 7 d2 6 d1 5 d0 4 sda 15 scl 14 a2 3 a1 2 a0 1 l12 3.3uh 805 c58 330pf 805 c60 330pf 805 r23 75 805 c59 .1uf 805 l5 3.3uh 805 c47 .1uf 805 c26 330pf 805 c48 330pf 805 c49 .1uf 805 r2 330 805 c14 .1uf 805 c15 .1uf 805 c8 .1uf 805 c17 .1uf 805 fb3 60 ohm 1210 fb4 60 ohm 1210 fb6 60 ohm 1210 fb5 60 ohm 1210 fb9 60 ohm 1210 fb7 60 ohm 1210 fb8 60 ohm 1210 l2 33uh 43fs c81 100uf c098 16v + c76 .1uf 805 50v u12 78l09 to-92 in 3 ref 2 out 1 c72 1uf a 16v + c84 .47uf-t a 35v + r54 2.2k 805 c96 .33uf 1206 50v r14 43k 805 c21 1uf b 16v + r8 3.9k 805 c41 3.3uf b 25v + c42 .047uf 1206 50v r9 3k 805 c23 2700pf 805 r10 3.3k 805 r11 200k 805 r19 10k 805 50v r20 10k 805 50v r26 10k 805 50v r27 10k 805 50v u6 mc14052b 16soic inh 6 a 10 b 9 x0 12 x1 14 x2 15 x3 11 y0 1 y1 5 y2 2 y3 4 xo 13 yo 3 vdd 16 vss 8 vee 7 jp4 header 4 4x1hdr 1 2 3 4 fb1 60 ohm sm121 0 fb2 60 ohm sm1210 u7 cxa1734s 30sdip sda 1 scl 2 dgnd 3 agnd 17 vcc 15 sad 4 vgr 5 iref 6 mainin 7 mainout 8 plint 9 stfil 10 compin 11 saptc 12 subout 13 stin 14 noisetc 16 sapout 18 sapin 19 ve 20 vewgt 21 vetc 22 veout 23 vcain 24 vcawgt 25 vcatc 26 itime 27 rout 28 lout 29 nc 30 c71 10uf radiala 50v + c77 10uf radiala 50v + c78 10uf radiala 50v + c73 .22uf-t a 35v + c79 4.7uf radiala 50v + c75 10uf radiala 50v + c80 10uf radiala 50v + c44 4.7uf radiala 50v + c43 10uf radiala 50v + c24 10uf radiala 50v + c22 10uf radiala 50v + c40 10uf radiala 50v + c39 10uf radiala 50v + c52 4.7uf radiala 50v + c70 4.7uf radiala 50v + c10 4.7uf radiala 50v + c11 4.7uf radiala 50v + c74 4.7uf radiala 50v + c12 100pf 805 50v c9 100pf 805 50v c7 10pf 805 50v c6 10pf 805 50v r24 1k 805 r48 option 1k 805 not installed r55 330 805 c46 100pf 805 50v c45 100pf 805 50v c38 10uf radiala 50v + c51 .1uf 805 50v l7 33uh 43fs r56 4.7k 805 r28 62k 805 tp3 tp hdr1x1 1 tp1 tp hdr1x1 1 tp2 tp hdr1x1 1 y2 35.46895 hc49 y3 28.63636 hc49 r52 10k 805 50v r53 10k 805 50v r84 vaopt 33 805 c83 4.7uf radiala 50v + evideo* blank* dclk p[0..7] rst* i2cdat video1 video2 i2cclk vref i2cdat i2cclk i2cclk i2cdat
bt829a/827a v ideostr eam ii decoders 72 pc b oard l ayout c onsiderations sample sc hematics l829a_b figure 46a. bt829/s3 vir g e 8-bit interface sc hematic - video input detail a a b b c c d d e e 4 4 3 3 2 2 1 1 composite video connector monday, march 25, 1996 85-000114-00-0 a bt829 - s3 8bit b 1 2 wednesday, october 16, 1996 title size document number rev date: sheet of mu x2 mu x1 cin lumm a cr oma c10 0.1u f 0805 j1 rca jack see spec 2 1 3 r8 75 ohm 0805 1 2 r9 75 ohm 0805 1 2 c11 0.1u f 0805 r1 0 75 ohm 0805 1 2 c12 0.1u f 0805
73 pc b oard l ayout c onsiderations sample sc hematics l829a_b bt829a/827a v ideostr eam ii decoders figure 46b. bt829/s3 vir g e 8-bit interface sc hematic - bt829 detail a a b b c c d d e e 4 4 3 3 2 2 1 1 decoder wednesday, october 04, 1995 85-000114-00-0 a bt829 - s3 8bit b 2 2 wednesday, october 16, 1996 title size document number rev date: sheet of vs ( 204) llc (148) spd (206) mux1 spc lk (205) mux2 re set hs (203) ci n ld7 (202) ld6 (184) ld5 (175) ld4 (174) ld3 (155) ld2 (154) ld1 (147) ld0 (146) vcc vcc vc c vc c c4 0.1u f 0805 r5 30k 0805 1 2 r6 30 k 080 5 1 2 c3 0.1u f 080 5 r3 1m 0805 1 2 c2 0.1u f 080 5 c5 0.1 uf 080 5 c6 0.1 uf 080 5 r4 2.2 k 0805 1 2 y1 28.63 636 se e spec c1 0.1u f 0805 c8 0.1 uf 0805 c7 22pf 080 5 r7 1m 080 5 1 2 l1 2.7uh 10% 0805 c9 33 pf 080 5 r1 2. 2k 0805 1 2 r2 2.2 k 0805 1 2 y1 35 .46895 mhz se e spec c8 0.1 uf 0805 c7 22pf 080 5 r7 1m 080 5 1 2 l1 2.2uh 10% 0805 c9 33 pf 0805 u1 10 0pqfp bt829 bt827 rst 15 va a 48 agnd 61 vd15 2 vd14 3 vd13 4 vd12 5 vd11 6 vd10 7 vd9 8 vd8 9 vd7 22 vd6 23 vd5 24 vd4 25 vd3 26 vd2 27 vd1 28 vd0 29 field 78 va a 65 tdo 32 ci n 67 mux1 57 mux0 55 syn cdet 59 yre f+ 49 yr ef- 62 tdi 37 tms 36 tck 34 xt0i 12 xt0 o 13 xt1i 16 xt1 o 17 gnd 11 gnd 21 gnd 31 gnd 77 gnd 81 gnd 93 va a 44 agnd 47 agnd 54 agnd 56 agnd 58 va a 60 agnd 66 muxout 53 refo ut 43 cbflag 89 hreset 82 vreset 79 active 83 dvalid 84 clkx1 97 clkx2 99 vd d 1 vd d 10 vd d 20 vd d 30 vd d 38 vd d 76 numxtal 80 vd d 92 trst 35 sda 18 scl 19 oe 98 i2ccs 14 yin 52 yabias 51 ydbias 50 ycbias 46 mux2 45 vpos 40 vneg 42 agcc ap 41 gnd 85 ccvalid 87 vactive 86 gnd 33 pwrdn 91 qclk 94 cre f+ 64 cleve l 74 cabias 70 ccbias 69 nc 68 cdbias 63 cr ef- 73 agnd 71 va a 72 agnd 75 vd d 88 gnd 90 vd d 96 gnd 10 0 gnd 39 gnd 95
bt829a/827a v ideostr eam ii decoders 74 pc b oard l ayout c onsiderations sample sc hematics l829a_b figure 47a. bt829/t rident v ga interface sc hematic - tv t uner and video input detail a a b b c c d d e e 4 4 3 3 2 2 1 1 vafc standard feature connector extended feature connector video interface wednesday, october 04, 1995 85-000112-00-0 a bt trident2 b 1 3 tuesday, july 01, 1997 title size document number rev date: sheet of px[0:15] yscl ysda yvs yhs yclk xsd a sda ysda px 0 px 8 px 6 px 7 px 9 px11 px 2 px 5 px 4 px 1 px 3 px1 3 px1 0 px1 4 px15 px12 xsc l scl yscl xsc l xsd a xhs xvs px13 px15 px 8 px14 px12 px11 px10 px 9 px 0 px 1 px 2 px 3 px 4 px 5 px 6 px 7 xcl k px 7 px1 4 px 5 px 3 px 2 px9 px 0 px 6 px1 1 px1 0 px1 2 px1 5 px 1 px1 3 px 8 px 4 sda scl hr eset vre set vre set hr eset qclk qclk +12 v vc c vcc +12 v +1 2v j5 con10 b 1 2 3 4 5 6 7 8 9 10 con2 io ch_80 n1 1 n2 2 n3 3 n4 4 n5 5 n6 6 n7 7 n8 8 n9 9 n10 10 n11 11 n12 12 n13 13 n29 29 m2 42 m3 43 m4 44 m5 45 m6 46 m7 47 m8 48 m9 49 m10 50 m11 51 m12 52 m13 53 n14 14 n15 15 n16 16 n17 17 n18 18 n19 19 n20 20 n21 21 n22 22 n23 23 n24 24 n25 25 n26 26 n27 27 n28 28 m14 54 m15 55 m16 56 m17 57 m18 58 m19 59 m20 60 m21 61 m22 62 m23 63 m24 64 m25 65 m26 66 m27 67 m28 68 m1 41 m29 69 m30 70 m31 71 m32 72 m33 73 m34 74 m35 75 m36 76 m37 77 m38 78 m39 79 m40 80 n30 30 n31 31 n32 32 n33 33 n34 34 n35 35 n36 36 n37 37 n38 38 n39 39 n40 40 con 1 ioch_26 y1 1 y2 2 y3 3 y4 4 y5 5 y6 6 y7 7 y8 8 y9 9 y10 10 y11 11 y12 12 y13 13 z1 14 z2 15 z3 16 z4 17 z5 18 z6 19 z7 20 z8 21 z9 22 z1 0 23 z1 1 24 z1 2 25 z1 3 26 c5 3 10uf 6032 c8 2 0.1u f 080 5 c8 1 0.1 uf 080 5 c8 0 0.1 uf 080 5 c7 9 0.1 uf 080 5 c7 8 0.1 uf 080 5 c7 6 0.1 uf 080 5 c7 5 0.1 uf 080 5 c7 4 0.1 uf 080 5 c7 3 0.1 uf 080 5 c7 2 0.1 uf 080 5 c7 1 0.1 uf 080 5 c7 7 0.1 uf 080 5 r3 2 080 5 33 1 2 r3 3 080 5 33 1 2 r3 0 080 5 33 1 2 r3 1 080 5 33 1 2 r3 5 0805 33 1 2 r3 6 080 5 33 1 2 r3 7 0805 33 1 2 r3 8 0805 33 1 2 r3 9 0805 33 1 2 con 3 ioch_20 y1 1 y2 2 y3 3 y4 4 y5 5 y6 6 y7 7 y8 8 y9 9 y10 10 z1 11 z2 12 z3 13 z4 14 z5 15 z6 16 z7 17 z8 18 z9 19 z1 0 20 r3 4 0805 33 1 2 c5 4 10u f 603 2 c5 5 10uf 603 2 c5 6 10uf 603 2 c57 10uf 6032 c5 2 10uf 603 2 c50 10uf 6032 c84 10uf 6032 c8 5 0.1u f 0805 j4 con10b 1 2 3 4 5 6 7 8 9 10
75 pc b oard l ayout c onsiderations sample sc hematics l829a_b bt829a/827a v ideostr eam ii decoders figure 47b. bt829/t rident v ga interface sc hematic - bt829 detail a a b b c c d d e e 4 4 3 3 2 2 1 1 33 oh m 16 places 0805 r49 - r64 decoder wednesday, october 04, 1995 85-000112-00-0 a bt trident2 b 2 3 tuesday, july 01, 1997 title size document number rev date: sheet of rst px1 3 px4 px1 0 px7 sd a px8 px1 5 px1 px9 px3 sc l px5 px1 1 px1 4 px0 px6 px1 2 px2 hr eset qclk tu ner_video comp osite_video vre set vcc vc c vc c c6 1 0.1u f 0805 r4 3 30 k 080 5 1 2 c6 0 0.1u f 080 5 r4 0 1m 0805 1 2 c6 2 0.1 uf 080 5 y2 28.63 636 se e spec c6 4 22pf 080 5 l5 2.7uh 10% 0805 c6 6 33 pf 0805 c58 0.1u f 0805 1 2 1 2 r4 6 2. 2k 080 5 1 2 1 2 1 2 1 2 r4 1 2.2 k 0805 1 2 r4 4 1m 080 5 1 2 1 2 1 2 1 2 r4 8 2. 2k 080 5 1 2 1 2 1 2 1 2 c6 3 0.1 uf 080 5 r4 2 30k 0805 1 2 c6 5 0.1 uf 0805 1 2 1 2 1 2 r4 7 2.2 k 080 5 1 2 c5 9 0.1u f 080 5 1 2 1 2 u1 10 0pqfp bt829 rst 15 va a 48 agnd 61 vd15 2 vd14 3 vd13 4 vd12 5 vd11 6 vd10 7 vd9 8 vd8 9 vd7 22 vd6 23 vd5 24 vd4 25 vd3 26 vd2 27 vd1 28 vd0 29 field 78 va a 65 tdo 32 ci n 67 mux1 57 mux0 55 syn cdet 59 yre f+ 49 yr ef- 62 tdi 37 tms 36 tck 34 xt0i 12 xt0 o 13 xt1i 16 xt1 o 17 gnd 11 gnd 21 gnd 31 gnd 77 gnd 81 gnd 93 va a 44 agnd 47 agnd 54 agnd 56 agnd 58 va a 60 agnd 66 muxout 53 refo ut 43 cbflag 89 hreset 82 vreset 79 active 83 dvalid 84 clkx1 97 clkx2 99 vd d 1 vd d 10 vd d 20 vd d 30 vd d 38 vd d 76 numxtal 80 vd d 92 trst 35 sda 18 scl 19 oe 98 i2ccs 14 yin 52 yabias 51 ydbias 50 ycbias 46 mux2 45 vpos 40 vneg 42 agcc ap 41 rden 85 aef 87 aff 86 gnd 33 clkin 91 qclk 94 cre f+ 64 cleve l 74 cabias 70 ccbias 69 nc 68 cdbias 63 cr ef- 73 agnd 71 va a 72 agnd 75 frst 88 gnd 90 vd d 96 gnd 10 0 gnd 39 gnd 95
bt829a/827a v ideostr eam ii decoders 76 pc b oard l ayout c onsiderations sample sc hematics l829a_b figure 47c. bt829/t rident v ga interface sc hematic - feature connector detail a a b b c c d d e e 4 4 3 3 2 2 1 1 composite video connector tv tuner 33 volt dc - dc converter wednesday, october 04, 1995 85-000112-00-0 a bt trident2 b 3 3 tuesday, july 01, 1997 title size document number rev date: sheet of ain tuner_video comp osite_video sc l sda hr eset sc l sda vcc +12 v +1 2v -12v r7 10k c2 3 22u f 734 3 fb2 c3 9 2.2 uf 3528 c70 0.1u f 0805 .68uf 1 6v 321 6 c6 7 + r6 5 330 o hms 080 5 1 2 j1 rca jack r6 6 1k 080 5 1 2 j3 r6 7 75 080 5 1 2 u3 tda8 425 in2l 1 vc ap 2 in2r 3 vc c 4 agn d 5 basr 6 bss r 7 tr er 8 outr 9 dgnd 10 sda 11 scl 12 outl 13 trel 14 basl 15 bssl 16 psu2 17 in1l 18 psu1 19 in1r 20 j2 phonejack stere o r21 100 ohm 0805 1 2 c8 3 1uf 16v 321 6 + r1 8 22k 080 5 1 2 d2 mmbz52 57bt1 sot -23 3 1 c2 0 10uf 25v 7343 + r2 0 2. 2k 0805 1 2 d1 bav99l t1 sot -23 1 2 3 q1 mmbt3904l t1 so t-23 3 2 1 u7 vi deo_tuner bi g_tuner temi c vt 11 +5vb 12 scl 13 sda 14 as 15 nc 21 ifsoun d 22 vide o_out 23 +5v if 24 audi o_out 25 gnd1 gnd2 gnd3 gnd4 c2 1 10uf 25v 734 3 + c2 2 6800p f 080 5 c25 22uf 7343 c3 2 22uf 7343 c3 3 22uf 7343 c3 8 2.2 uf 352 8 c24 0.1u f 0805 c3 4 0.0 15uf 0805 c3 1 0.0 33uf 0805 c3 0 5600p f 080 5 c37 5600p f 080 5 c36 0. 033uf 080 5 c3 5 0.0 15uf 0805
77 l829a_b c ontrol r egister d efinitions this section describes the function of the v arious control re gisters. t able 13 summarizes of the re gister functions and follo ws with details of each re gister . t ab le 13. register map (1 of 2) register name mnemonic register ad dress 640 x 480 square pix el ntsc (default) 768 x 576 square pix el p al/secam 720 x 480 ccir ntsc 720 x 576 ccir p al/secam 320 x 240 2:1 ntsc (square pix el, cif) 320 x 288 2:1 p al/secam (square pix el, cif) de vice status st a tus 0x00 0x00 0x00 0x00 0x00 0x00 0x00 input f or mat iform 0x01 0x58 0x78 0x58 0x78 0x58 0x78 t empor al decimation tdec 0x02 0x00 0x00 0x00 0x00 0x00 0x00 msb cropping cr op 0x03 0x12 0x23 0x12 0x23 0x11 0x21 v er tical dela y , lo w er byte vdela y_lo 0x04 0x16 0x16 0x16 0x16 0x16 0x16 v er tical activ e , lo w er byte v a ctive_lo 0x05 0xe0 0x40 0xe0 0x40 0xe0 0x40 hor iz ontal dela y , lo w er byte hdela y_lo 0x06 0x78 0x9a 0x80 0x90 0x40 0x48 hor iz ontal activ e , lo w er byte ha ctive_lo 0x07 0x80 0x00 0xd0 0xd0 0x40 0x80 hor iz ontal scaling, upper byte hscale_hi 0x08 0x02 0x03 0x00 0x05 0x11 0x1a hor iz ontal scaling, lo w er byte hscale_lo 0x09 0xa c 0x3c 0xf8 0x04 0xf0 0x09 br ightness control bright 0x0a 0x00 0x00 0x00 0x00 0x00 0x00 miscellaneous control contr ol 0x0b 0x20 0x20 (1) 0x20 0x20 (1) 0x20 0x20 luma gain, lo w er byte (contr ast) contrast_lo 0x0c 0xd8 0xd8 0xd8 0xd8 0xd8 0xd8 chroma (u) gain, lo w er byte (satur ation) sa t_u_lo 0x0d 0xfe 0xfe 0xfe 0xfe 0xfe 0xfe chroma (v) gain, upper byte (satur ation) sa t_v_lo 0x0e 0xb4 0xb4 0xb4 0xb4 0xb4 0xb4 hue control hue 0x0f 0x00 0x00 0x00 0x00 0x00 0x00 sc loop control scloop 0x10 0x00 0x00 (1) 0x00 0x00 (1) 0x00 0x00
bt829a/827a v ideostr eam ii decoders 78 c ontrol r egister d efinitions l829a_b white cr ush up count wc_up 0x11 0xcf 0xcf 0xcf 0xcf 0xcf 0xcf output f or mat oform 0x12 0x06 0x06 0x06 0x06 0x06 0x06 v er tical scaling, upper byte vscale_hi 0x13 0x60 0x60 0x60 0x60 0x40 (2) 0x40 (2) v er tical scaling, lo w er byte vscale_lo 0x14 0x00 0x00 0x00 0x00 0x00 0x00 t est control test 0x15 0x01 0x01 0x01 0x01 0x01 0x01 video timing p olar ity register vpole 0x16 0x00 0x00 0x00 0x00 0x00 0x00 id code idcode 0x17 0x70 0x70 0x70 0x70 0x70 0x70 a gc dela y adela y 0x18 0x68 0x7f 0x68 0x7f 0x68 0x7f burst gate dela y bdela y 0x19 0x5d 0x72 (1) 0x5d 0x72 (1) 0x5d 0x72 adc interf ace adc 0x1a 0x82 0x82 0x82 0x82 0x82 0x82 video timing control vtc 0x1b 0x00 0x00 0x00 0x00 0x00 0x00 extended data ser vices/closed caption status cc_st a tus 0x1c 0x00 0x00 0x00 0x00 0x00 0x00 extended data ser vices/closed caption data cc_d a t a 0x1d 0x00 0x00 0x00 0x00 0x00 0x00 white cr ush do wn count wc_dn 0x1e 0x7f 0x7f 0x7f 0x7f 0x7f 0x7f softw are reset sreset 0x1f prog r ammab le i/o p_io 0x3f secam video register diff erences miscellaneous control contr ol 0x00 0x00 sc loop control scloop 0x10 0x10 burst gate dela y bdela y 0xa0 0xa0 notes: (1). secam video register differences to pal video. (2). when using one eld, no additional v er tical scaling is necessar y f or cif resolutions . the int bit in register 0xb(vscale_hi) should be set to a logical z ero when scaling from only one eld. t ab le 13. register map (2 of 2) register name mnemonic register ad dress 640 x 480 square pix el ntsc (default) 768 x 576 square pix el p al/secam 720 x 480 ccir ntsc 720 x 576 ccir p al/secam 320 x 240 2:1 ntsc (square pix el, cif) 320 x 288 2:1 p al/secam (square pix el, cif)
79 c ontrol r egister d efinitions 0x00 ?de vice status register (st a tus) l829a_b bt829a/827a v ideostr eam ii decoders 0x00 ?de vice status register (st a tus) this control re gister may be written to or read by the mpu at an y time. upon reset it is initialized to 0x00. cof is the least signi cant bit. the cof and lof status bits hold their v alues until reset to their def ault v alues by writing to them. the other six bits do not hold their v alues, b ut continually output the status. an asterisk indicates the def ault op- tion. pres v ideo present status. v ideo is determined as not present when an input sync is not detected in 31 consecuti v e line periods. 0* = v ideo not present 1 = v ideo present hloc de vice in h-lock. if hsync is found within 1 clock c ycle of the e xpected posi- tion of hsync for 32 consecuti v e lines, this bit is set to a logical 1. once set, if hsync is not found within 1 clock c ycle of the e xpected position of hsync for 32 consecuti v e lines, this bit is set to a logical 0. mpu writes to this bit are ignored. this bit indicates the stability of the incoming video. while it is an indicator of horizontal locking, some video sources will characteristically v ary from line to line by more than one clock c ycle so that this bit will ne v er be set. consumer vcrs are e xamples of sources that will tend to ne v er set this bit. 0* = de vice not in h-lock 1 = de vice in h-lock field field status. this bit re ects whether an odd or e v en eld is being decoded. the field bit is determined by the relationship between hreset and vreset . 0* = odd eld 1 = ev en eld numl number of lines. this bit identi es the number of lines found in the video stream. this bit is used to determine the type of video input to the bt829a. thirty-tw o con- secuti v e elds with the same number of lines is required before this status bit will change. 0* = 525 line format (ntsc/p al-m) 1 = 625 line format (p al/secam) 7 6 5 4 3 2 1 0 pres hloc field numl csel ccv alid lof cof 0 0 0 0 0 0 0 0
bt829a/827a v ideostr eam ii decoders 80 c ontrol r egister d efinitions 0x00 ?de vice status register (st a tus) l829a_b csel crystal select. this bit identi es which crystal port is selected. when automatic format detection is enabled, this bit will be the same as numl. 0* = xt al0 input selected 1 = xt al1 input selected ccv alid v alid closed caption data. this bit indicates that v alid closed caption or e xtended data services (eds) sample pairs ha v e been stored in the closed caption data re g- isters. this bit indicates that the closed caption data fifo is half full. it is reset af- ter being written into or a chip reset occurs. lof luma adc ov er o w . on po wer -up, this bit is set to 0. if an adc o v er o w occurs, the bit is set to a logical 1. it is reset after being written to or a chip reset occurs. the state of this bit is not v alid and should be ignored when the adc is in po w- er -do wn mode (y_sleep = 1). when the luma a/d is in sleep mode, lof is set to 1. cof chroma adc ov er o w . on po wer -up, this bit is set to 0. if an adc o v er o w oc- curs, the bit is set to a logical 1. it is reset after being written to or a chip reset oc- curs. the state of this bit is not v alid and should be ignored when the adc is in po wer -do wn mode (c_sleep = 1). when the chroma a/d is in sleep mode, cof is set to 1.
81 c ontrol r egister d efinitions 0x01 ?input format register (iform) l829a_b bt829a/827a v ideostr eam ii decoders 0x01 ?input format register (iform) this control re gister may be written to or read by the mpu at an y time. upon reset it is initialized to 0x58. for- ma t(0) is the least signi cant bit. an asterisk indicates the def ault option. ha ctive when using the bt829a with a pack ed memory architecture, for e xample, with eld memories, this bit should be programmed with a logical 1. when implement- ing a vram based architecture, program with a logical 0. 0* = reset ha ctive with hreset 1 = extend ha ctive be yond hreset muxsel used for softw are control of video input selection. the bt829a can select between four composite video sources, or three composite and one s-v ideo source. 00 = select mux3 input to muxout 01 = select mux2 input to muxout 10* = select mux0 input to muxout 11 = select mux1 input to muxout xtsel if automatic format detection is required, logical 11 must be loaded. logical 01 and 10 are used if softw are format selection is desired. 00 = reserv ed 01 = select xt0 input (only xt0 present) 10 = select xt1 input (both xts present) 11* = auto xt select enabled (both xts present) forma t automatic format detection may be enabled or disabled. the numl bit is used to determine the input format when automatic format detection is enabled. 000* = auto format detect enabled 001 = ntsc (m) input format 010 = ntsc with no pedestal format 011 = p al (b, d, g, h, i) input format 100 = p al (m) input format 101 = p al (n) input format 110 = secam input format 111 = p al (ncombination) input format 7 6 5 4 3 2 1 0 ha ctive muxsel xtsel forma t 0 1 0 1 1 0 0 0
bt829a/827a v ideostr eam ii decoders 82 c ontrol r egister d efinitions 0x02 ? t emporal decimation register (tdec) l829a_b 0x02 ? t emporal decimation register (tdec) this control re gister may be written to or read by the mpu at an y time. upon reset it is initialized to 0x00. dec_ra t(0) is the least signi cant bit. this re gister enables temporal decimation by discarding a nite number of elds or frames from the incoming video. an asterisk indicates the def ault option. dec_field de nes whether decimation is by elds or frames. 0* = decimate frames 1 = decimate elds fld align this bit aligns the start of decimation with an e v en or odd eld. 0* = start decimation on the odd eld (an odd eld is the rst eld dropped). 1 = start decimation on the e v en eld (an e v en eld is the rst eld dropped). dec_ra t dec_ra t is the number of elds or frames dropped out of 60 ntsc or 50 p al/secam elds or frames. 0x00 v alue disables decimation (all video frames and elds are output). no te: use caution when changing the programming in the tdec re gister . 0x00 must be loaded before the decimation v alue. this will ensure decimation does not start on the wrong eld or frame. the re gister should not be load- ed with greater than 60 (0x3c) for ntsc, or 50 (0x34) for p al/secam. xx00 0000?x11 1111 = number of elds/frames dropped. 7 6 5 4 3 2 1 0 dec_field fld align dec_ra t 0 0 0 0 0 0 0 0
83 c ontrol r egister d efinitions 0x03 ?msb cr opping register (cr op) l829a_b bt829a/827a v ideostr eam ii decoders 0x03 ?msb cr opping register (cr op) this control re gister may be written to or read by the mpu at an y time. upon reset it is initialized to 0x12. ha ctive_msb(0) is the least signi cant bit. see the v a ctive, vdela y , ha ctive and hdela y re gisters for descriptions on the operation of this re gister . vdela y_msb 00xx xxxx?1xx xxxx = the most signi cant tw o bits of v ertical delay re gister . v a ctive_msb xx00 xxxx?x11 xxxx = the most signi cant tw o bits of v ertical acti v e re gister . hdela y_msb xxxx 00xx?xxx 11xx = the most signi cant tw o bits of horizontal delay re gister . ha ctive_msb xxxx xx00?xxx xx11 = the most signi cant tw o bits of horizontal acti v e re gister . 7 6 5 4 3 2 1 0 vdela y_msb v a ctive_msb hdela y_msb ha ctive_msb 0 0 0 1 0 0 1 0
bt829a/827a v ideostr eam ii decoders 84 c ontrol r egister d efinitions 0x04 ? v er tical dela y register , lo wer byte (vdela y_lo) l829a_b 0x04 ? v er tical dela y register , lo wer byte (vdela y_lo) this control re gister may be written to or read by the mpu at an y time. upon reset it is initialized to 0x16. vdela y_lo(0) is the least signi cant bit. this 8-bit re gister is the lo wer byte of the 10-bit vdela y re gister . the tw o msbs of vdela y are contained in the cr op re gister . vdela y de nes the number of half lines between the trailing edge of vreset and the start of acti v e video. vdela y_lo 0x01?xff = the least signi cant byte of the v ertical delay re gister . 7 6 5 4 3 2 1 0 vdela y_lo 0 0 0 1 0 1 1 0
85 c ontrol r egister d efinitions 0x05 ? v er tical active register , lo wer byte (v a ctive_lo) l829a_b bt829a/827a v ideostr eam ii decoders 0x05 ? v er tical active register , lo wer byte (v a ctive_lo) this control re gister may be written to or read by the mpu at an y time, and upon reset it is initialized to 0xe0. v a ctive_lo(0) is the least signi cant bit. this 8-bit re gister is the lo wer byte of the 10-bit v a ctive re gister . the tw o msbs of v a ctive are contained in the cr op re gister . v a ctive de nes the number of lines used in the v ertical scaling process. the actual number of lines output by the bt829a is scaling_ra tio * v a ctive. v a ctive_lo 0x00?xff = the least signi cant byte of the v ertical acti v e re gister . 7 6 5 4 3 2 1 0 v a ctive_lo 1 1 1 0 0 0 0 0
bt829a/827a v ideostr eam ii decoders 86 c ontrol r egister d efinitions 0x06 ?horizontal dela y register , lo wer byte (hdela y_lo) l829a_b 0x06 ?horizontal dela y register , lo wer byte (hdela y_lo) this control re gister may be written to or read by the mpu at an y time. upon reset it is initialized to 0x78. hdela y_lo(0) is the least signi cant bit. this 8-bit re gister is the lo wer byte of the 10-bit hdela y re gister . the tw o msbs of hdela y are contained in the cr op re gister . hdela y de nes the number of scaled pix els between the f alling edge of hreset and the start of acti v e video. hdela y_lo 0x01?xff = the least signi cant byte of the horizontal delay re gister . ha ctive pix els will be output by the chip starting at the f all of hreset . caution: hdela y must be programmed with an e v en number . 7 6 5 4 3 2 1 0 hdela y_lo 0 1 1 1 1 0 0 0
87 c ontrol r egister d efinitions 0x07 ?horizontal active register , lo wer byte (ha ctive_lo) l829a_b bt829a/827a v ideostr eam ii decoders 0x07 ?horizontal active register , lo wer byte (ha ctive_lo) this control re gister may be written to or read by the mpu at an y time. upon reset it is initialized to 0x80. ha ctive_lo(0) is the least signi cant bit. ha ctive de nes the number of horizontal acti v e pix els per line output by the bt829a. ha ctive_lo 0x00?xff = the least signi cant byte of the horizontal acti v e re gister . this 8-bit re gister is the lo wer byte of the 10-bit ha ctive re gister . the tw o msbs of ha ctive are contained in the cr op re gister . 7 6 5 4 3 2 1 0 ha ctive_lo 1 0 0 0 0 0 0 0
bt829a/827a v ideostr eam ii decoders 88 c ontrol r egister d efinitions 0x08 ?horizontal scaling register , upper byte (hscale_hi) l829a_b 0x08 ?horizontal scaling register , upper byte (hscale_hi) this control re gister may be written to or read by the mpu at an y time. upon reset it is initialized to 0x02. this 8-bit re gister is the upper byte of the 16-bit hscale re gister . hscale_hi 0x00?xff = the most signi cant byte of the horizontal scaling ratio. 7 6 5 4 3 2 1 0 hscale_hi 0 0 0 0 0 0 1 0
89 c ontrol r egister d efinitions 0x09 ?horizontal scaling register , lo wer byte (hscale_lo) l829a_b bt829a/827a v ideostr eam ii decoders 0x09 ?horizontal scaling register , lo wer byte (hscale_lo) this control re gister may be written to or read by the mpu at an y time. upon reset it is initialized to 0xa c. this 8-bit re gister is the lo wer byte of the 16-bit hscale re gister . hscale_lo 0x00?xff = the least signi cant byte of the horizontal scaling ratio. 7 6 5 4 3 2 1 0 hscale_lo 1 0 1 0 1 1 0 0
bt829a/827a v ideostr eam ii decoders 90 c ontrol r egister d efinitions 0x0a ?brightness contr ol register (bright) l829a_b 0x0a ?brightness contr ol register (bright) the brightness control in v olv es the addition of a tw o s complement number to the luma channel. brightness can be adjusted in 255 steps, from ?28 to +127. the resolution of brightness change is one lsb (0.39% with respect to the full luma range). an asterisk indicates the def ault option. bright 7 6 5 4 3 2 1 0 bright 0 0 0 0 0 0 0 0 he x v alue binar y v alue brightness chang ed by number of lsbs p er cent of full scale 0x80 1000 0000 ?28 ?00% 0x81 1000 0001 ?27 ?9.22% . . . . . . 0xff 1111 1111 ?1 ?.78% 0x00* 0000 0000* 00 0% 0x01 0000 0001 +01 +0.78% . . . . . . 0x7e 0111 1110 +126 +99.2% 0x7f 0111 1111 +127 +100%
91 c ontrol r egister d efinitions 0x0b ?miscellaneous contr ol register (contr ol) l829a_b bt829a/827a v ideostr eam ii decoders 0x0b ?miscellaneous contr ol register (contr ol) this control re gister may be written to or read by the mpu at an y time, and upon reset it is initialized to 0x20. sa t_v_msb is the least signi cant bit. an asterisk indicates the def ault option. lno tch this bit is used to include the luma notch lter . f or monochrome video, the notch should not be used. this will output full bandwidth luminance. 0* = enable the luma notch lter 1 = disable the luma notch lter comp when comp is set to logical one, the luma notch is disabled. when comp is set to logical zero, the c adc is disabled. 0* = composite v ideo 1 = y/c component v ideo ldec the luma decimation lter is used to reduce the high-frequenc y component of the luma signal. useful when scaling to cif resolutions or lo wer . 0 = enable luma decimation using selectable h lter 1* = disable luma decimation cbsense this bit controls whether the rst pix el of a line is a cb pix el or a cr pix el. f or e x- ample, if cbsense is lo w and hdela y is an e v en number , the rst acti v e pix el output is a cb pix el. if hdela y is odd, cbsense may be programmed high to produce a cb pix el as the rst acti v e pix el output. 0* = normal cb, cr order 1 = in v ert cb, cr order reser ved this bit should only be written with a logical zero. con_msb the most signi cant bit of the luma g ain (contrast) v alue. sa t_u_msb the most signi cant bit of the chroma (u) g ain v alue. sa t_v_msb the most signi cant bit of the chroma (v) g ain v alue. 7 6 5 4 3 2 1 0 lno tch comp ldec cbsense reser v ed con_msb sa t_u_msb sa t_v_msb 0 0 1 0 0 0 0 0
bt829a/827a v ideostr eam ii decoders 92 c ontrol r egister d efinitions 0x0c ?luma gain register , lo wer byte (contrast_lo) l829a_b 0x0c ?luma gain register , lo wer byte (contrast_lo) this control re gister may be written to or read by the mpu at an y time. upon reset it is initialized to 0xd8. contrast_lo(0) is the least signi cant bit. the con_l_msb bit and the contrast_lo re gister concatenate to form the 9-bit contrast re gister . the v alue in this re gister is multiplied by the luminance v alue to pro vide con- trast adjustment. contrast_lo the least signi cant byte of the luma g ain (contrast) v alue. 7 6 5 4 3 2 1 0 contrast_lo 1 1 0 1 1 0 0 0 decimal v alue he x v alue % of original signal 511 0x1ff 236.57% 510 0x1fe 236.13% . . . . . . 217 0x0d9 100.46% 216 0x0d8 100.00% . . . . . . 128 0x080 59.26% . . . . . . 1 0x001 0.46% 0 0x000 0.00%
93 c ontrol r egister d efinitions 0x0d ?chr oma (u) gain register , lo wer byte (sa t_u_lo) l829a_b bt829a/827a v ideostr eam ii decoders 0x0d ?chr oma (u) gain register , lo wer byte (sa t_u_lo) this control re gister may be written to or read by the mpu at an y time. upon reset it is initialized to 0xfe. sa t_u_lo(0) is the least signi cant bit. sa t_u_msb in the contr ol re gister , and sa t_u_lo concatenate to gi v e a 9-bit re gister (sa t_u). this re gister is used to add a g ain adjustment to the u component of the video signal. by adjusting the u and v color components of the video stream by the same amount, the saturation is adjusted. f or normal saturation adjustment, the g ain in both the color dif ference paths must be the same (i.e. the ratio between the v alue in the u g ain re gister and the v alue in the v g ain re gister should be k ept constant at the def ault po wer -up ratio). when changing the saturation, if the sa t_u_msb bit is altered, care must be tak en to ensure that the other bits in the contr ol re gister are not af fected. sa t_u_lo 7 6 5 4 3 2 1 0 sa t_u_lo 1 1 1 1 1 1 1 0 decimal v alue he x v alue % of original signal 511 0x1ff 201.18% 510 0x1fe 200.79% . . . . . . 255 0x0ff 100.39% 254 0x0fe 100.00% . . . . . . 128 0x080 50.39% . . . . . . 1 0x001 0.39% 0 0x000 0.00%
bt829a/827a v ideostr eam ii decoders 94 c ontrol r egister d efinitions 0x0e ?chr oma (v) gain register , lo wer byte (sa t_v_lo) l829a_b 0x0e ?chr oma (v) gain register , lo wer byte (sa t_v_lo) this control re gister may be written to or read by the mpu at an y time. upon reset it is initialized to 0xb4. sa t_v_lo(0) is the least signi cant bit. sa t_v_msb in the contr ol re gister and sa t_v_lo concatenate to gi v e a 9-bit re gister (sa t_v). this re gister is used to add a g ain adjustment to the v component of the video signal. by adjusting the u and v color components of the video stream by the same amount, the saturation is adjusted. f or normal saturation adjustment, the g ain in both the color dif ference paths must be the same (i.e. the ratio between the v alue in the u g ain re gister and the v alue in the v g ain re gister should be k ept constant at the def ault po wer -up ratio). when changing the saturation, if the sa t_v_msb bit is altered, care must be tak en to ensure that the other bits in the contr ol re gister are not af fected. sa t_v_lo 7 6 5 4 3 2 1 0 sa t_v_lo 1 0 1 1 0 1 0 0 decimal v alue he x v alue % of original signal 511 0x1ff 283.89% 510 0x1fe 283.33% . . . . . . 181 0x0b5 100.56% 180 0x0b4 100.00% . . . . . . 128 0x080 71.11% . . . . . . 1 0x001 0.56% 0 0x000 0.00%
95 c ontrol r egister d efinitions 0x0f ?hue contr ol register (hue) l829a_b bt829a/827a v ideostr eam ii decoders 0x0f ?hue contr ol register (hue) this control re gister may be written to or read by the mpu at an y time. upon reset it is initialized to 0x00. hue(0) is the least signi cant bit. hue adjustment in v olv es the addition of a tw o s complement number to the demodulating subcarrier phase. hue can be adjusted in 256 steps in the range ?0? to +89.3?, in increments of 0.7?. an asterisk in- dicates the def ault option. hue 7 6 5 4 3 2 1 0 hue 0 0 0 0 0 0 0 0 he x v alue binar y v alue subcarrier ref erence chang ed by resulting hue chang ed by 0x80 1000 0000 ?0? +90? 0x81 1000 0001 ?9.3? +89.3? . . . . . . . . 0xff 1111 1111 ?.7? +0.7? 0x00* 0000 0000 00? 00? 0x01 0000 0001 +0.7? ?.7? . . . . . . . . 0x7e 0111 1110 +88.6? ?8.6? 0x7f 0111 1111 +89.3? ?9.3?
bt829a/827a v ideostr eam ii decoders 96 c ontrol r egister d efinitions 0x10 ? sc loop contr ol (scloop) l829a_b 0x10 ? sc loop contr ol (scloop) this control re gister may be written to or read by the mpu at an y time. upon reset it is initialized to 0x00. a ccel is the least signi cant bit. an asterisk indicates the def ault option. peak this bit determines if the normal luma lo w pass lters are implemented via the hfil t bits or if the peaking lters are implemented. the ldec bit in the control re gister must be programmed to zero to use these lters. 0* = normal luma lo w pass ltering 1 = use luma peaking lters ca gc this bit controls the chroma a gc function. when enabled, chroma a gc will compensate for non-standard chroma le v els. the compensation is achie v ed by multiplying the incoming chroma signal by a v alue in the range of 0.5 to 2.0. 0* = chroma a gc disabled 1 = chroma a gc enabled ckill this bit determines whether the lo w color detector and remo v al circuitry is en- abled. 0* = lo w color detection and remo v al disabled 1 = lo w color detection and remo v al enabled 7 6 5 4 3 2 1 0 peak ca gc ckill hfil t reser v ed 0 0 0 0 0 0 0 0
97 c ontrol r egister d efinitions 0x10 ? sc loop contr ol (scloop) l829a_b bt829a/827a v ideostr eam ii decoders hfil t these bits control the con guration of the optional 6-tap horizontal lo w-p ass fil- ter . the auto-format mode determines the appropriate lo w-pass lter based on the horizontal scaling ratio selected. the ldec bit in the contr ol re gister must be programmed to zero to use these lters. 00* = auto f ormat. if auto format is selected when horizontally scaling between full resolution and half resolution, no ltering is selected. when scaling between one-half and one-third resolution, the cif lter is used. when scaling between one-third and one-se v enth resolution, the qcif lter is used, and at less than one-se v enth resolution, the icon lter is used. 01 = cif 10 = qcif (when decoding secam video this lter must be enabled) 11 = icon if the peak bit is set to logical one, the hfil t bits determine which peaking lter is selected. 00 = maximum peaking response 01 = medium peaking response 10 = lo w peaking response 11 = minimum peaking response reser ved these bits must be set to zero.
bt829a/827a v ideostr eam ii decoders 98 c ontrol r egister d efinitions 0x11 ? white crush up count register (wc_up) l829a_b 0x11 ? white crush up count register (wc_up) this control re gister may be written to or read by the mpu at an y time, and upon reset it is initialized to 0xcf . upcnt(0) is the least signi cant bit. majs these bits determine the majority comparison point for the white crush up func- tion. 00 = 3/4 of maximum luma v alue 01 = 1/2 of maximum luma v alue 10 = 1/4 of maximum luma v alue 11* = automatic upcnt the v alue programmed in these bits accumulates once per eld or frame, in the case where the majority of the pix els in the acti v e re gion of the image are belo w a selected v alue. the accumulated v alue determines the e xtent to which the a gc v alue needs to be raised in order to k eep the sync le v el proportionate with the white le v el. the upcnt v alue is assumed positi v e, i.e., 3f = 63 3e = 62 : : : . . . 00 = 0 7 6 5 4 3 2 1 0 majs upcnt 1 1 0 0 1 1 1 1
99 c ontrol r egister d efinitions 0x12 ?output format register (oform) l829a_b bt829a/827a v ideostr eam ii decoders 0x12 ?output format register (oform) this control re gister may be written to or read by the mpu at an y time. upon reset it is initialized to 0x06. oes(0) is the least signi cant bit. an asterisk indicates the def ault option. range luma output range: this bit determines the range for the luminance output on the bt829a. the range must be limited when using the control codes as video timing. 0* = normal operation (luma range 16?53, chroma range 2?53). y=16 is black (pedestal) cr , cb=128 is zero color information 1 = full-range output (luma range 0?55, chroma range 2?53) y=0 is black (pedestal) cr , cb=128 is zero color information core luma coring: these bits control the coring v alue used by the bt829a. when cor - ing is acti v e and the total luminance le v el is belo w the limit programmed into these bits, the luminance signal is truncated to zero. 00* = 0x00 no coring 01 = 8 10 = 16 11 = 32 vbi_frame this bit enables the vbi frame output mode. in the vbi frame output mode, e v ery line consists of un ltered 8*fsc non-image data. this bit supersedes bit vbien in the vtc re gister . vbifmt (also in vtc) w orks in both vbi frame and line out- put modes. 0* = vbi frame output mode disabled 1 = vbi frame output mode enabled code code control disable: this bit determines if control codes are output with the vid- eo data. spi mode 2 requires this bit to be programmed with a logical 1. when con- trol codes are inserted into the data stream, the e xternal control signals are still a v ailable. 0* = disable control code insertion 1 = enable control code insertion 7 6 5 4 3 2 1 0 range core vbi_frame code len oes 0 0 0 0 0 1 1 0
bt829a/827a v ideostr eam ii decoders 100 c ontrol r egister d efinitions 0x12 ?output format register (oform) l829a_b len 8- or 16-bit f ormat: this bit determines the output data format. in 8-bit mode, the data is output on vd[15:8]. 0 = 8-bit ycrcb 4:2:2 output stream 1* = 16-bit ycrcb 4:2:2 output stream oes oes[1] and oes[0] control the output three-states when the oe pin or the out - en bit (vpole bit 7) is asserted. the pins are di vided into three groups: timing ( hreset , vreset , a ctive, v a ctive, cbfla g, d v alid and field), clocks (clkx1, clkx2 and qclk) and data (vd[15:0]). ccv alid cannot out- put three-states. 00 = three-state timing and data only 01 = three-state data only 10 = three-state timing, data and clocks 11 = three-state clocks and data only y/cr/cb[7] y/cr/cb[0] y[7] y[0] vd[15] vd[8] vd[7] vd[0] cr/cb[7] cr/cb[0] vd 16-bit 8-bit
101 c ontrol r egister d efinitions 0x13 ? v er tical scaling register , upper byte (vscale_hi) l829a_b bt829a/827a v ideostr eam ii decoders 0x13 ? v er tical scaling register , upper byte (vscale_hi) this control re gister may be written to or read by the mpu at an y time. upon reset it is initialized to 0x60. an asterisk indicates the def ault option. ycomb luma comb enable: when enabled, the luma comb lter performs a weighted a v- erage on 2, 3, 4, or 5 lines of luminance data. the coef cients used for the a v erage are x ed and no interpolation is performed. the number of lines used for the luma comb lter is determined by the vfil t bits in the vtc re gister . when disabled by a logical zero, ltering and full v ertical interpolation is performed based upon the v alue programmed into the vscale re gister . the luma comb lter cannot be enabled on the BT827A. 0* = v ertical lo w-pass ltering and v ertical interpolation 1 = v ertical lo w-pass ltering only comb chroma comb enable: this bit determines if the chroma comb is included in the data path. if enabled, a full line store is used to a v erage adjacent lines of color in- formation, reducing cross-color artif acts. 0 = chroma comb disabled 1* = chroma comb enabled int interlace: this bit is programmed to indicate if the incoming video is interlaced or non-interlaced. f or e xample, if using the full frame as input for v ertical scaling, this bit should be programmed high. if using a single eld for v ertical scaling, this bit should be programmed lo w . single eld scaling is normally used when scaling belo w cif resolution and outputting to a non-interlaced monitor . using a single eld will reduce motion artif acts. 0 = non-interlace vs 1* = interlace vs vscale_hi v ertical scaling ratio: these v e bits represent the most signi cant portion of the 13-bit v ertical scaling ratio re gister . the system must tak e care not to alter the con- tents of the line, comb and int bits while adjusting the scaling ratio. 7 6 5 4 3 2 1 0 ycomb comb int vscale_hi 0 1 1 0 0 0 0 0
bt829a/827a v ideostr eam ii decoders 102 c ontrol r egister d efinitions 0x14 ? v er tical scaling register , lo wer byte (vscale_lo) l829a_b 0x14 ? v er tical scaling register , lo wer byte (vscale_lo) this control re gister may be written to or read by the mpu at an y time. upon reset it is initialized to 0x00. vscale_lo v ertical scaling ratio: these eight bits represent the least signi cant byte of the 13-bit v ertical scaling ratio re gister . the y are concatenated with v e bits in vscale_hi. the follo wing equation should be used to determine the v alue for this re gister: f or e xample, to scale p al/secam input to square pix el qcif , the total number of v ertical lines is 156: 7 6 5 4 3 2 1 0 vscale_lo 0 0 0 0 0 0 0 0 vscale = ( 0x10000 ?{ [ ( scaling_ratio ) ?1] * 512 } ) & 0x1fff vscale = ( 0x10000 ?{ [ ( 4/1 ) ? ] * 512 } ) & 0x1fff = 0x1a00
103 c ontrol r egister d efinitions 0x15 ? t est contr ol register (test) l829a_b bt829a/827a v ideostr eam ii decoders 0x15 ? t est contr ol register (test) this control re gister is reserv ed for putting the part into test mode. write operation to this re gister may cause unde- termined beha vior and should not be attempted. a read c ycle from this re gister returns 0x01, and only a write of 0x01 is permitted.
bt829a/827a v ideostr eam ii decoders 104 c ontrol r egister d efinitions 0x16 ? video timing p olarity register (vpole) l829a_b 0x16 ? video timing p olarity register (vpole) this control re gister may be written to or read by the mpu at an y time. upon reset, it is initialized to 0x00. an asterisk indicates the def ault option. outen three-states the pins de ned by oes in the oform re gister . the af fected pins are: vd[15:0], hreset , vreset , a ctive, v a ctive, d v alid, cbfla g, field, qclk, clkx1, and clkx2. when pin 85 is a logical zero 0* = enable outputs 1 = three-state outputs when pin 85 is a logical one 0* = three-state outputs 1 = enable outputs d v alid 0* = d v alid pin: acti v e high 1 = d v alid pin: acti v e lo w v a ctive 0* = v a ctive pin: acti v e high 1 = v a ctive pin: acti v e lo w cbfla g 0* = cbfla g pin: acti v e high 1 = cbfla g pin: acti v e lo w field 0* = field pin: high indicates odd eld 1 = field pin: high indicates e v en eld a ctive 0* = a ctive pin: acti v e high 1 = a ctive pin: acti v e lo w hreset 0* = hreset pin: acti v e lo w 1 = hreset pin: acti v e high vreset 0* = vreset pin: acti v e lo w 1 = vreset pin: acti v e high 7 6 5 4 3 2 1 0 out_en d v alid v a ctive cbfla g field a ctive hreset vreset 0 0 0 0 0 0 0 0
105 c ontrol r egister d efinitions 0x17 ?id code register (idcode) l829a_b bt829a/827a v ideostr eam ii decoders 0x17 ?id code register (idcode) this control re gister may be read by the mpu at an y time. p ar t_rev(0) is the least signi cant bit. p ar t_id 1110 = bt829a p art id code 1100 = BT827A p art id code p ar t_rev 0x0 ?0xf = current re vision id code 7 6 5 4 3 2 1 0 p ar t_id p ar t_rev 1 1 1 0 0 0 0 0
bt829a/827a v ideostr eam ii decoders 106 c ontrol r egister d efinitions 0x18 ?a gc dela y register (adela y) l829a_b 0x18 ?a gc dela y register (adela y) this control re gister may be written to or read by the mpu at an y time. upon reset, it is initialized to 0x68. adela y a gc g ate delay for back-porch sampling. the follo wing equation should be used to determine the v alue for this re gister: f or e xample, for an ntsc input signal: 7 6 5 4 3 2 1 0 adela y 0 1 1 0 1 0 0 0 adelay = ( 6.8 m s * f clkx1 ) + 7 adelay = ( 6.8 m s * 14.32 mhz ) + 7 = 104 (0x68)
107 c ontrol r egister d efinitions 0x19 ?bur st dela y register (bdela y) l829a_b bt829a/827a v ideostr eam ii decoders 0x19 ?bur st dela y register (bdela y) this control re gister may be written to or read by the mpu at an y time. upon reset, it is initialized to 0x5d. bde- la y(0) is the least signi cant bit. bdela y the b urst g ate delay for sub-carrier sampling. the follo wing equation should be used to determine the v alue for this re gister: f or e xample, for an ntsc input signal: 7 6 5 4 3 2 1 0 bdela y 0 1 0 1 1 1 0 1 bdelay = ( 6.5 m s * f clkx1 ) bdelay = ( 6.5 m s * 14.32 mhz ) = 93 (0x5d)
bt829a/827a v ideostr eam ii decoders 108 c ontrol r egister d efinitions 0x1a ?adc interface register (adc) l829a_b 0x1a ?adc interface register (adc) this control re gister may be written to or read by the mpu at an y time. upon reset, it is initialized to 0x82. reserv ed is the least signi cant bit. an asterisk indicates the def ault option. reser ved these bits should only be written with bit 7 a logical one and bit 6 a logical zero. sync_t this bit de nes the v oltage le v el belo w which the sync signal can be detected. 0* = analog syncdet threshold high (~125 mv) 1 = analog syncdet threshold lo w (~75 mv) a gc_en this bit controls the a gc function. if disabled, refout is not dri v en and an e x- ternal reference v oltage must be pro vided. if enabled, refout is dri v en to control the a/d reference v oltage. 0* = a gc enabled 1 = a gc disabled clk_sleep when this bit is at a logical one, the system clock is po wered do wn, b ut the output clocks (clkx1 and clkx2) are still running, and the i 2 c re gisters are still acces- sible. reco v ery time is approximately one second. 0* = normal clock operation 1 = shut do wn the system clock (po wer do wn) y_sleep this bit enables putting the luma adc in sleep mode. 0* = normal y adc operation 1 = sleep y adc operation c_sleep this bit enables putting the chroma adc in sleep mode. 0 = normal c adc operation 1* = sleep c adc operation cr ush this bit enables white crush mode, and must be written with a logical zero. 0* = normal sync le v el to white le v el 1 = enable white cr ush mode to compensate for nonstandard sync to white video relationship 7 6 5 4 3 2 1 0 reser v ed sync_t a gc_en clk_sleep y_sleep c_sleep cr ush 1 0 0 0 0 0 1 0
109 c ontrol r egister d efinitions 0x1b ? video timing contr ol (vtc) l829a_b bt829a/827a v ideostr eam ii decoders 0x1b ? video timing contr ol (vtc) this re gister may be written to or read by the mpu at an y time. upon reset, it is initialized to 0x00. vfil t(0) is the least signi cant bit. an asterisk indicates the def ault option. hsfmt this bit selects between a single-pix el-wide hreset and the standard 64-clock-wide hreset . 0* = hreset is 64 clkx1 c ycles wide 1 = hreset is 1 pix el wide a ctfmt this bit selects whether composite a ctive (ha ctive and v a ctive) or ha c- tive only is output on the a ctive pin. 0* = a ctive is composite acti v e 1 = a ctive is horizontal acti v e clkga te this bit selects the signals that are g ated with clk to create qclk. if logical zero is selected, the a ctive pin (composite a ctive or ha ctive) is used in g ating clk. 0* = clkx1 and clkx2 are g ated with d v alid and a ctive to create qclk. 1 = clkx1 and clkx2 are g ated with d v alid to create qclk. vbien this bit enables vbi data to be captured. 0* = do not capture vbi 1 = capture vbi vbifmt this bit determines the byte ordering for vbi data. 0* = pix el n on the vd[15:8] data b us, pix el n+1 on the vd[7:0] data b us. 1 = pix el n+1 on the vd[15:8] data b us, pix el n on the vd[7:0] data b us (pix el n refers to the 1st, 3rd, 5th..., while pix el n+1 refers to the 2nd, 4th, 6th in a horizontal line of video.) 7 6 5 4 3 2 1 0 hsfmt a ctfmt clkga te vbien vbifmt v alidfmt vfil t 0 0 0 0 0 0 0 0
bt829a/827a v ideostr eam ii decoders 110 c ontrol r egister d efinitions 0x1b ? video timing contr ol (vtc) l829a_b v alidfmt 0* = normal d v alid timing 1 = d v alid is the logical and of v alid and a ctive, where a ctive is controlled by the a ctfmt bit. also, the qclk signal will free turn and is an in v erted v ersion of clkx1 or clkx2, depending upon whether 8- or 16-bit pix el output format is selected. vfil t these bits control the number of taps in the v ertical scaling filter . the number of taps must be chosen in conjunction with the horizontal scale f actor to ensure the needed data does not o v er o w the internal fifo. if the ycomb bit in the vscale_hi re gister is a logical one, the follo wing settings and equations apply: 00* = 2-tap a v ailable at all resolutions. 01 = 3-tap only a v ailable if scaling to less than 385 horizontal acti v e pix els for p al or 361 for ntsc (cif or smaller). 10 = 4-tap only a v ailable if scaling to less than 193 horizontal acti v e pix els for p al or 181 for ntsc (qcif or smaller) 11 = 5-tap only a v ailable if scaling to less than 193 horizontal acti v e pix els for p al or 181 for ntsc (qcif or smaller). if the ycomb bit in the vscale_hi re gister is a logical zero, the follo wing settings and equations apply: 00* = 2-tap interpolation only . a v ailable at all resolutions. 01 = 2-tap and 2-tap interpolation. only a v ailable if scaling to less than 385 horizontal acti v e pix els for p al or 361 for ntsc (cif or smaller). 10 = 3-tap and 2-tap interpolation. only a v ailable if scaling to less than 193 horizontal acti v e pix els for p al or 181 for ntsc (qcif or smaller). 11 = 4-tap and 2-tap interpolation. only a v ailable if scaling to less than 193 horizontal acti v e pix els for p al or 181 for ntsc (qcif or smaller). no te: the BT827A can only be used with a vfil t v alue of 00, as it does not ha v e a v ertical scaling lter . 1 2 - - - 1 z 1 + ( ) 1 4 - - - 1 2 z 1 z 2 + + ( ) 1 8 - - - 1 3 z 1 3 z 2 z 3 + + + ( ) 1 16 - - - - - - 1 4 z 1 6 z 2 4 z 3 z 4 + + + + ( ) 1 2 - - - 1 z 1 + ( ) 1 4 - - - 1 2 z 1 z 2 + + ( ) 1 8 - - - 1 3 z 1 3 z 2 z 3 + + + ( )
111 c ontrol r egister d efinitions 0x1c ?extended data ser vice/closed caption status register l829a_b bt829a/827a v ideostr eam ii decoders 0x1c ?extended data ser vice/closed caption status register (cc_st a tus) this re gister may be written or read by the mpu at an y time. upon reset, the v alue of re gister bits 7, 1, and 0 are in- determinate because their status depends on the incoming cc/eds data. ha ving re gister bits 6, 5 and 4 at their reset v alue causes the cc/eds circuitry to be po wered do wn. lo _hi is the least signi cant bit. an asterisk indicates the def ault option. p arity_err this bit corresponds to the current w ord in cc_d a t a. 0 = no error 1 = odd parity error no te: closed caption data is transmitted using odd parity . ccv alid_en this bit serv es as a mask for the ccv alid interrupts pin. 0 = disabled ccv alid interrupts pin 1 = enabled ccv alid interrupts pin eds this bit determines if eds data is written into the cc_d a t a fifo. 0* = eds data is not written into the cc_d a t a fifo 1 = eds data is written into the cc_d a t a fifo cc this bit determines if cc data is written into the cc_d a t a fifo. 0* = cc data is not written into the cc_d a t a fifo 1 = cc data is written into the cc_d a t a fifo or this bit indicates the cc_d a t a fifo is full and eds or cc data has been lost. this bit is read only . on reset or read of cc_d a t a this bid is set to zero. 0 = an o v er o w has not occurred since this bit w as last reset 1 = an o v er o w has occurred d a cc/eds data a v ailable. this bit indicates if there is v alid data in the cc_d a t a fifo. this bit is read only . on reset, this bit is set to zero. 0 = fifo is empty 1 = one or more bytes a v ailable 7 6 5 4 3 2 1 0 p arity_err ccv alid_en eds cc or d a cc _eds lo _hi x 1 0 0 0 0 x x
bt829a/827a v ideostr eam ii decoders 112 c ontrol r egister d efinitions 0x1c ?extended data ser vice/closed caption status regis- l829a_b cc _eds this bit indicates if a cc byte or an eds byte is in the cc_d a t a re gister . after the cc_d a t a re gister is read, this bit is automatically updated. this bit is read only . on reset, this bit is not v alid. 0 = closed caption byte in cc_d a t a 1 = extended data service byte in cc_d a t a lo _hi cc/eds data are output in 16-bit w ords. this bit indicates whether the lo w or high byte is in the cc_d a t a re gister . this bit is read only . on reset, this bit is not v alid. 0 = lo w byte is in the cc_d a t a re gister 1 = high byte is in the cc_d a t a re gister
113 c ontrol r egister d efinitions 0x1d ?extended data ser vice/closed caption data register l829a_b bt829a/827a v ideostr eam ii decoders 0x1d ?extended data ser vice/closed caption data register (cc_d a t a) this re gister is read only . it may be read by the mpu at an y time. writes to this re gister will be ignored. upon reset, the v alue of the bits in this re gister are indeterminate because their status depends on the incoming cc/eds data. cc_d a t a(0) is the least signi cant bit. cc_d a t a the lo w or high data byte transmitted in a closed caption or e xtended data service line. 7 6 5 4 3 2 1 0 cc_d a t a x x x x x x x x
bt829a/827a v ideostr eam ii decoders 114 c ontrol r egister d efinitions 0x1e ? white crush do wn count register (wc_dn) l829a_b 0x1e ? white crush do wn count register (wc_dn) this control re gister may be written to or read by the mpu at an y time, and upon reset is initialized to 0x7f . dncnt(0) is the least signi cant bit. this re gister is programmed with a tw o s compliment number . ver ten 0* = normal operation 1 = adds v ertical detection algorithm to reject noise causing f alse v ertical syncs. wcframe this bit programs the rate at which the dncnt and upcnt v alues are accumu- lated. 0 = once per eld 1 = once per frame dncnt the v alue programmed in these bits accumulates once per eld or frame. the ac- cumulated v alue determines the e xtent to which the a gc v alue needs to be lo w- ered in order to k eep the sync le v el proportionate to the white le v el. the dncnt v alue is assumed ne g ati v e, i.e., 3f = ? 3e = ? : : : . . . 00 = ?4 7 6 5 4 3 2 1 0 ver ten wcframe dncnt 0 1 1 1 1 1 1 1
115 c ontrol r egister d efinitions 0x1f ?software reset register (sreset) l829a_b bt829a/827a v ideostr eam ii decoders 0x1f ?software reset register (sreset) this command re gister can be written at an y time. read c ycles to this re gister return an unde ned v alue. a data write c ycle to this re gister resets the de vice to the def ault state (indicated in the command re gister de nitions by an asterisk). writing an y data v alue into this address resets the de vice.
bt829a/827a v ideostr eam ii decoders 116 c ontrol r egister d efinitions 0x3f ?pr ogrammab le i/o register (p_io) l829a_b 0x3f ?pr ogrammab le i/o register (p_io) this control re gister may be written to or read by the mpu at an y time, and upon reset is initialized to 0x00. out_0 is the least signi cant bit. while in 8-bit output mode (spi-8), the vd[7:0] pins are completely asynchronous. in[3:0] represent the digital le v els input on vd[7:4], while the v alues programmed into out[3:0] are output onto vd[3:0] in[3:0] these input bits can be used to monitor e xternal signals from vd[7:4]. the pro- grammable i/o re gister is only accessible in the 8-bit 4:2:2 ycrcb output mode (len=0). if not in the 8-bit output mode, the v alues returned by the in[3:0] bits are not v alid. out[3:0] these output bits can be programmed to output miscellaneous additional signals from the video decoder on vd[3:0]. the programmable i/o re gister is only acces- sible in the 8-bit 4:2:2 ycrcb output mode. if not in the 8-bit output mode, the out[3:0] bits will be set to logical zero. 7 6 5 4 3 2 1 0 in_3 in_2 in_1 in_0 out_3 out_2 out_1 out_0 0 0 0 0 0 0 0 0
117 l829a_b p arametric i nformation dc electrical p arameter s t ab le 14. recommended operating conditions p arameter symbol min t yp max units p o w er supply ?analog v aa 4.75 5.00 5.25 v p o w er supply ?digital v dd 4.75 5.00 5.25 v maxim um d |v dd ? v aa | 0.5 v mux0, mux1 and mux2 input range (a c coupling required) 0.5 1.00 2.00 v vin amplitude range (ac coupling required) 0.5 1.00 2.00 v ambient oper ating t emper ature t a 0 +70 ?c t ab le 15. absolute maxim um ratings p arameter symbol min t yp max units v aa (measured to a gnd) 7.00 v v dd (measured to dgnd) 7.00 v v oltage on an y signal pin (see the note belo w) dgnd ?0.5 v dd + 0.5 v analog input v oltage a gnd ?0.5 v aa + 0.5 v stor age t emper ature t s ?5 +150 ?c j unction t emper ature t j +125 ?c v apor phase solder ing (15 seconds) t vsol +220 ?c note: stresses above those listed may cause permanent damage to the device. this is a stress rating only, and func- tional operation at these or any other conditions above those listed in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. this device employs high-impedance cmos devices on all signal pins. it must be handled as an esd-sensi- tive device. voltage on any signal pin that exceeds the power supply voltage by more than +0.5 v or drops below ground by more than 0.5 v can induce destructive latch-up.
bt829a/827a v ideostr eam ii decoders 118 p arametric i nformation dc electrical p arameter s l829a_b t ab le 16. dc characteristics p arameter symbol min t yp max units digital inputs input high v oltage (ttl) input lo w v oltage (ttl) input high v oltage (xt0i, xt1i) input lo w v oltage (xt0i, xt1i) input high current (v in =v dd ) input lo w current (v in =gnd) input capacitance (f=1 mhz, v in =2.4 v) v ih v il v ih v il i ih i il c in 2.0 3.5 gnd ?0.5 5 v dd + 0.5 0.8 v dd + 0.5 1.5 10 ?0 v v v v m a m a pf digital outputs output high v oltage (i oh = ?00 m a) output lo w v oltage (i ol = 3.2 ma) three-state current output capacitance v oh v ol i oz c o 2.4 5 v dd 0.4 10 v v m a pf analog pin input capacitance c a 5 pf
119 p arametric i nformation a c electrical p arameter s l829a_b bt829a/827a v ideostr eam ii decoders a c electrical p arameter s t ab le 17. cloc k timing p arameter s (1 of 2) p arameter symbol min t yp max units ntsc: clkx1 rate clkx2 rate (50 ppm source required) f s1 f s2 14.318181 28.636363 mhz mhz p al/secam: clkx1 rate clkx2 rate (50 ppm source required) f s1 f s2 17.734475 35.468950 mhz mhz xt0 and xt1 inputs cycle time high time lo w time 1 2 3 28.2 12 12 ns ns ns
bt829a/827a v ideostr eam ii decoders 120 p arametric i nformation a c electrical p arameter s l829a_b clkx1 duty cycle clkx2 duty cycle clkx2 to clkx1 dela y clkx1 to data dela y clkx2 to data dela y clkx1 (f alling edge) to qclk (rising edge) clkx2 (f alling edge) to qclk (rising edge) 8-bit mode (1) data to qclk (rising edge) dela y qclk (rising edge) to data dela y 16-bit mode (1) data to qclk (rising edge) dela y qclk (rising edge) to data dela y 4 5 6 41 42 7b 8b 7a 8a 45 40 0 3 3 0 0 5 15 14 25 55 60 2 11 11 8 8 % % ns ns ns ns ns ns ns ns ns notes: (1). because qclk is generated with a gated version of clkx1 or clkx2, the timing in symbols 7 and 8 are sub- ject to changes in the duty cycle of clkx1 and clkx2. if crystals are used as clock sources for the bt829a, the duty cycle is symmetric. this assumption is used to generate the timing numbers shown in 7 and 8. for non-symmetric clock sources, use the following equations: t ab le 17. cloc k timing p arameter s (2 of 2) p arameter symbol min t yp max units data to qclk (setup) (16-bit mode) xtal per iod + clkx1 to qclk (max) - clkx1 to data (max) or symbol 1 + symbol 41 (max) - symbol 5 (max) ntsc: 34.9 ns + 8 ns - 11 ns = 31.9 ns p al: 28.2 ns + 8 ns -11 ns = 25.2 ns qclk to data (hold) (16-bit mode) xtal per iod - clkx1 to qclk (min) + clkx1 to data (min) or symbol 1 - symbol 41 (min) + symbol 5 (min) ntsc: 34.9 ns - 0 ns + 3 ns = 37.9 ns p al: 28.3 ns - 0 ns + 3 ns = 31.3 ns data to qclk (setup) (8-bit mode) (xtal per iod)/2 + clkx2 to qclk (max) - clkx2 to data (max) or (symbol 1)/2 + symbol 42 (max) - symbol 6 (max) ntsc: 17.5 ns + 8ns - 11 ns = 14.5 ns p al: 14.1 ns + 8 ns - 11 ns = 11.1 ns qclk to data (hold) (8-bit mode) (xtal per iod)/2 - clkx2 to qclk (min) + clkx2 to data (min) or (symbol 1)/2 - symbol 42 (min) + symbol 6 (min) ntsc: 17.5 ns - 0 ns + 3 ns = 20.5 ns p al: 14.1 ns - 0 ns + 3 ns = 17.1 ns
121 p arametric i nformation a c electrical p arameter s l829a_b bt829a/827a v ideostr eam ii decoders figure 48. cloc k timing dia gram xt0i clkx2 or xt1i clkx1 pix el and control data 1 2 3 4 6 5 qclk pix el and control data qclk 8a 7a 16-bit mode 8-bit mode 42 41 8b 7b t ab le 18. p o wer suppl y current p arameter s p arameter symbol min t yp max units supply current v aa =v dd =5.0v , f clkx2 =28.64 mhz, t=25?c v aa =v dd =5.25v , f clkx2 =35.47 mhz, t=70?c v aa =v dd =5.25v , f clkx2 =35.47 mhz, t=0?c supply current, p o w er do wn i 170 65 250 280 ma ma ma ma t ab le 19. output enab le timing p arameter s p arameter symbol min t yp max units oe asser ted to data bus dr iv en oe asser ted to data v alid oe negated to data bus not dr iv en 9 10 11 0 100 100 ns ns ns rst lo w time 8 xt al cycles
bt829a/827a v ideostr eam ii decoders 122 p arametric i nformation a c electrical p arameter s l829a_b figure 49. output enab le timing dia gram oe 10 11 pix el, cloc k and control data 9 t ab le 20. jt a g timing p arameter s p arameter symbol min t yp max units tms , tdi setup time tms , tdi hold time tck asser ted to tdo v alid tck asser ted to tdo dr iv en tck negated to tdo three-stated tck lo w time tck high time 12 13 14 15 16 17 18 25 25 10 10 60 5 80 ns ns ns ns ns ns ns figure 50. jt a g timing dia gram 12 13 17 18 14 15 16 tdi, tms tck tdo t ab le 21. decoder p erf ormance p arameter s p arameter symbol min t yp max units hor iz ontal loc k range 7 % of line length fsc , loc k-in range 800 hz gain range ? 6 db note: test conditions (unless otherwise specified): ?ecommended operating conditions.?ttl input values are 0? v, with input rise/fall times 3 ns, measured between the 10% and 90% points. timing reference points at 50% for digital inputs and outputs. pixel and control data loads 30 pf and 3 10 pf. clkx1 and clkx2 loads 50 pf. con- trol data includes cbflag, dvalid, active, vactive, hreset , vreset and field.
123 p arametric i nformation p ac ka g e mec hanical dra wings l829a_b bt829a/827a v ideostr eam ii decoders p ac ka g e mec hanical dra wings figure 51. 100-pin tqfp p ac ka g e mec hanical dra wing
bt829a/827a v ideostr eam ii decoders 124 p arametric i nformation p ac ka g e mec hanical dra wings l829a_b figure 52. 100-pin pqfp p ac ka g e mec hanical dra wing
125 p arametric i nformation re vision histor y l829a_b bt829a/827a v ideostr eam ii decoders re vision histor y t ab le 22. bt829a datasheet re vision histor y re vision date description a 01/24/97 engineer ing release b 11/97 clar i cation of functional diff erences betw een the bt829a and bt829 products . remo v al of bt825a video decoder inf or mation.
url address www .nb.rockwell.com e-mail address literature@nb.rockwell.com for more information: call 1-800-854-8099 international information: call 1-714-221-6996 headquarters rockwell semiconductor systems inc. 4311 jamboree road, p .o. box c newport beach, ca 92658-8902 phone: (714) 221-4600 fax: (714) 221-6375 european headquarters rockwell semiconductor systems s.a.r.l. les t aissounieres b1 1680 route des dolines bp 283 06905 sophia antipolis cedex france phone: 00.33.4.93.00.33.35 fax: 00.33.4.93.00.33.03 asia pacific headquarters 1, kallang sector , #07-04/06 kolam a yer industrial park singapore, 1334 phone: 011-65-841-3801 fax: 011-65-841-3802 us southwest phone: (714) 222-9119 fax: (714) 222-0620 us los angeles phone: (805) 376-0559 fax: (805) 376-8180 us south central phone: (972) 479-9310 fax: (972) 479-9317 us southeast phone: (770) 393-1830 fax: (770) 395-1419 us florida/south america phone: (813) 538-8837 fax: (813) 531-3031 us northwest phone: (408) 249-9696 fax: (408) 249-6518 us north central phone: (630) 773-3454 fax: (630) 773-3907 us northeast phone: (508) 692-7660 fax: (508) 692-8185 europe mediterranean phone: (39-2) 93179911 fax: (39-2) 93179913 europe north phone: (44-1) 344 486444 fax: (44-1) 344 486555 europe south phone: (33-1) 49 06 39 80 fax: (33-1) 49 06 39 90 europe central phone: (49-89) 829-1320 fax: (49-89) 834-2734 australia phone: (61-2) 9869-4088 direct fax: (61-2) 9869-4077 hong kong phone: (852) 2 827-0181 fax: (852) 2 827-6488 japan phone: (81-3) 5371 1551 fax: (81-3) 5371 1501 korea phone: (82-2) 565-2880 fax: (82-2) 565-1440 singapore phone: (65) 737-7355 fax: (65) 737-9077 t aiwan phone: (886-2) 720-0282 fax: (886-2) 757-6760 l829a_b printed in usa

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